From d92de1d9477635806344ce1167c68915df8c909d Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 29 Mar 2024 17:22:53 -0400 Subject: [PATCH 01/10] OpcodeDispatcher: drop result masking for shifts flag calcs are fine with upper garbage. Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 7 ------- 1 file changed, 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 4ddd687d9..bb60aed7d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1574,10 +1574,6 @@ void OpDispatchBuilder::SHLOp(OpcodeArgs) { OrderedNode *Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); StoreResult(GPRClass, Op, Result, -1); - if (Size < 32) { - Result = _Bfe(OpSize::i32Bit, Size, 0, Result); - } - if constexpr (SHL1Bit) { GenerateFlags_ShiftLeftImmediate(Op, Result, Dest, 1); } @@ -1784,9 +1780,6 @@ void OpDispatchBuilder::SHRDOp(OpcodeArgs) { StoreResult(GPRClass, Op, Res, -1); - if (Size != 64) { - Res = _Bfe(OpSize::i64Bit, Size, 0, Res); - } GenerateFlags_ShiftRight(Op, Res, Dest, Shift); } From 8cc684fa127118d79b7d95db0fcf0eba1587cae8 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 2 Apr 2024 08:45:49 -0400 Subject: [PATCH 02/10] OpcodeDispatcher: drop misinformed comment tbnz only tests a single bit, not a mask. Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index bb60aed7d..7cd27b25e 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1662,13 +1662,7 @@ void OpDispatchBuilder::SHLDOp(OpcodeArgs) { const auto Size = GetSrcBitSize(Op); - // x86 masks the shift by 0x3F or 0x1F depending on size of op. Arm will mask - // by 0x3F when we do 64-bit shifts so we don't need to mask in that case, - // since the modulo is preserved even after presubtracting Size=64 for - // ShiftRight. - // - // TODO: Implement this optimization, it requires turning the shift=0 cases - // into (shift&0xc0) bit tests which is a bit complicated for now. + // x86 masks the shift by 0x3F or 0x1F depending on size of op. if (Size == 64) { Shift = _And(OpSize::i64Bit, Shift, _Constant(0x3F)); } else { From 2abac03ab0d6b8fd689694747e7a5a16d3e40d36 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:21:23 -0400 Subject: [PATCH 03/10] OpcodeDispatcher: add LoadConstantShift helper shows up a bunch Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 13 +++++++++++++ FEXCore/Source/Interface/Core/OpcodeDispatcher.h | 1 + 2 files changed, 14 insertions(+) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 7cd27b25e..e61afb266 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1546,6 +1546,19 @@ void OpDispatchBuilder::CPUIDOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RCX, _Bfe(OpSize::i64Bit, 32, 0, Result_Upper)); } +uint32_t OpDispatchBuilder::LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit) { + if (Is1Bit) { + return 1; + } else { + // x86 masks the shift by 0x3F or 0x1F depending on size of op + const uint32_t Size = GetSrcBitSize(Op); + uint64_t Mask = Size == 64 ? 0x3F : 0x1F; + + LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); + return Op->Src[1].Data.Literal.Value & Mask; + } +} + void OpDispatchBuilder::XGetBVOp(OpcodeArgs) { OrderedNode *Function = LoadGPRRegister(X86State::REG_RCX); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 46a268137..761464cae 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -329,6 +329,7 @@ public: void CMOVOp(OpcodeArgs); void CPUIDOp(OpcodeArgs); void XGetBVOp(OpcodeArgs); + uint32_t LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit); template void SHLOp(OpcodeArgs); void SHLImmediateOp(OpcodeArgs); From 582c3dae6e4df6fed18c05722687f49c5b07cf1f Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:21:55 -0400 Subject: [PATCH 04/10] OpcodeDispatcher: use LoadConstantShift for SHLD Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index e61afb266..ec1ad77a0 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1715,18 +1715,9 @@ void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) { OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); - - uint64_t Shift = Op->Src[1].Data.Literal.Value; + uint64_t Shift = LoadConstantShift(Op, false); const auto Size = GetSrcBitSize(Op); - // x86 masks the shift by 0x3F or 0x1F depending on size of op - if (Size == 64) { - Shift &= 0x3F; - } else { - Shift &= 0x1F; - } - if (Shift != 0) { OrderedNode *Res{}; if (Size < 32) { From cf26ec789893eeb7b9ebe46c148c82b2f093a4e0 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:22:14 -0400 Subject: [PATCH 05/10] OpcodeDispatcher: use LoadConstantShift for SHRD Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index ec1ad77a0..e0670ebb0 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1785,20 +1785,10 @@ void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) { OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); - - uint64_t Shift = Op->Src[1].Data.Literal.Value; + uint64_t Shift = LoadConstantShift(Op, false); const auto Size = GetSrcBitSize(Op); - // x86 masks the shift by 0x3F or 0x1F depending on size of op - if (Size == 64) { - Shift &= 0x3F; - } else { - Shift &= 0x1F; - } - if (Shift != 0) { - OrderedNode *Res{}; if (Size < 32) { OrderedNode *ShiftRight = _Constant(Shift); From 8c53a9f0514f5ddeccc0581630525faeb485e4b3 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:38:56 -0400 Subject: [PATCH 06/10] OpcodeDispatcher: use LoadConstantShift for rotates Signed-off-by: Alyssa Rosenzweig --- .../Source/Interface/Core/OpcodeDispatcher.cpp | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index e0670ebb0..ece22d25d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1872,16 +1872,13 @@ void OpDispatchBuilder::RotateOp(OpcodeArgs) { CalculateDeferredFlags(); auto LoadShift = [this, Op](bool MustMask) -> OrderedNode * { - // x86 masks the shift by 0x3F or 0x1F depending on size of op - const uint32_t Size = GetSrcBitSize(Op); - uint64_t Mask = Size == 64 ? 0x3F : 0x1F; - - if (Is1Bit) { - return _Constant(1); - } else if (IsImmediate) { - LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); - return _Constant(Op->Src[1].Data.Literal.Value & Mask); + if (Is1Bit || IsImmediate) { + return _Constant(LoadConstantShift(Op, Is1Bit)); } else { + // x86 masks the shift by 0x3F or 0x1F depending on size of op + const uint32_t Size = GetSrcBitSize(Op); + uint64_t Mask = Size == 64 ? 0x3F : 0x1F; + auto Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags, {.AllowUpperGarbage = true}); return MustMask ? _And(OpSize::i64Bit, Src, _Constant(Mask)) : Src; } From 2a9f1ce8cb0c491007f60308d1aa8987fb34e7a3 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:28:59 -0400 Subject: [PATCH 07/10] OpcodeDispatcher: unify imm/1-bit SHL Signed-off-by: Alyssa Rosenzweig --- .../Interface/Core/OpcodeDispatcher.cpp | 55 ++++++------------- .../Source/Interface/Core/OpcodeDispatcher.h | 2 +- 2 files changed, 18 insertions(+), 39 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index ece22d25d..b07d8b74a 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1571,45 +1571,24 @@ void OpDispatchBuilder::XGetBVOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RDX, Result_Upper); } -template void OpDispatchBuilder::SHLOp(OpcodeArgs) { - OrderedNode *Src{}; - OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - - if constexpr (SHL1Bit) { - Src = _Constant(1); - } - else { - Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags); - } const auto Size = GetSrcBitSize(Op); + auto Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); + auto Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags); OrderedNode *Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); StoreResult(GPRClass, Op, Result, -1); - if constexpr (SHL1Bit) { - GenerateFlags_ShiftLeftImmediate(Op, Result, Dest, 1); - } - else { - GenerateFlags_ShiftLeft(Op, Result, Dest, Src); - } + GenerateFlags_ShiftLeft(Op, Result, Dest, Src); } +template void OpDispatchBuilder::SHLImmediateOp(OpcodeArgs) { OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); - - uint64_t Shift = Op->Src[1].Data.Literal.Value; + uint64_t Shift = LoadConstantShift(Op, SHL1Bit); const auto Size = GetSrcBitSize(Op); - // x86 masks the shift by 0x3F or 0x1F depending on size of op - if (Size == 64) { - Shift &= 0x3F; - } else { - Shift &= 0x1F; - } - OrderedNode *Src = _Constant(Size, Shift); OrderedNode *Result = _Lshl(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); @@ -6058,54 +6037,54 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 1), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 2), 1, &OpDispatchBuilder::RCLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 3), 1, &OpDispatchBuilder::RCROp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 1), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 2), 1, &OpDispatchBuilder::RCLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 3), 1, &OpDispatchBuilder::RCROp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 1), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 2), 1, &OpDispatchBuilder::RCLOp1Bit}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 3), 1, &OpDispatchBuilder::RCROp8x1Bit}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 4), 1, &OpDispatchBuilder::SHLOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 5), 1, &OpDispatchBuilder::SHROp}, // 1Bit SHR - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 1), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 2), 1, &OpDispatchBuilder::RCLOp1Bit}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 3), 1, &OpDispatchBuilder::RCROp1Bit}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 4), 1, &OpDispatchBuilder::SHLOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 5), 1, &OpDispatchBuilder::SHROp}, // 1Bit SHR - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 1), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 2), 1, &OpDispatchBuilder::RCLSmallerOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 3), 1, &OpDispatchBuilder::RCRSmallerOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 4), 1, &OpDispatchBuilder::SHLOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 4), 1, &OpDispatchBuilder::SHLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 1), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 2), 1, &OpDispatchBuilder::RCLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 3), 1, &OpDispatchBuilder::RCROp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 4), 1, &OpDispatchBuilder::SHLOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 4), 1, &OpDispatchBuilder::SHLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR // GROUP 3 diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 761464cae..6d3126b38 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -330,8 +330,8 @@ public: void CPUIDOp(OpcodeArgs); void XGetBVOp(OpcodeArgs); uint32_t LoadConstantShift(X86Tables::DecodedOp Op, bool Is1Bit); - template void SHLOp(OpcodeArgs); + template void SHLImmediateOp(OpcodeArgs); template void SHROp(OpcodeArgs); From 031e756a789a219e30243b2c8084525d9487a00a Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:32:14 -0400 Subject: [PATCH 08/10] OpcodeDispatcher: unify imm/1-bit SHR Signed-off-by: Alyssa Rosenzweig --- .../Interface/Core/OpcodeDispatcher.cpp | 41 +++++-------------- .../Source/Interface/Core/OpcodeDispatcher.h | 2 +- 2 files changed, 11 insertions(+), 32 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index b07d8b74a..2ed6176f1 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1597,44 +1597,23 @@ void OpDispatchBuilder::SHLImmediateOp(OpcodeArgs) { GenerateFlags_ShiftLeftImmediate(Op, Result, Dest, Shift); } -template void OpDispatchBuilder::SHROp(OpcodeArgs) { - OrderedNode *Src; auto Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - - if constexpr (SHR1Bit) { - Src = _Constant(1); - } - else { - Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags); - } + auto Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags); auto ALUOp = _Lshr(IR::SizeToOpSize(std::max(4, GetSrcSize(Op))), Dest, Src); StoreResult(GPRClass, Op, ALUOp, -1); - if constexpr (SHR1Bit) { - GenerateFlags_ShiftRightImmediate(Op, ALUOp, Dest, 1); - } - else { - GenerateFlags_ShiftRight(Op, ALUOp, Dest, Src); - } + GenerateFlags_ShiftRight(Op, ALUOp, Dest, Src); } +template void OpDispatchBuilder::SHRImmediateOp(OpcodeArgs) { auto Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); - - uint64_t Shift = Op->Src[1].Data.Literal.Value; + uint64_t Shift = LoadConstantShift(Op, SHR1Bit); const auto Size = GetSrcBitSize(Op); - // x86 masks the shift by 0x3F or 0x1F depending on size of op - if (Size == 64) { - Shift &= 0x3F; - } else { - Shift &= 0x1F; - } - OrderedNode *Src = _Constant(Size, Shift); auto ALUOp = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Src); @@ -6038,7 +6017,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 2), 1, &OpDispatchBuilder::RCLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 3), 1, &OpDispatchBuilder::RCROp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR @@ -6047,7 +6026,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 2), 1, &OpDispatchBuilder::RCLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 3), 1, &OpDispatchBuilder::RCROp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR @@ -6056,7 +6035,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 2), 1, &OpDispatchBuilder::RCLOp1Bit}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 3), 1, &OpDispatchBuilder::RCROp8x1Bit}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 5), 1, &OpDispatchBuilder::SHROp}, // 1Bit SHR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, // 1Bit SHR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR @@ -6065,7 +6044,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 2), 1, &OpDispatchBuilder::RCLOp1Bit}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 3), 1, &OpDispatchBuilder::RCROp1Bit}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 5), 1, &OpDispatchBuilder::SHROp}, // 1Bit SHR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, // 1Bit SHR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR @@ -6074,7 +6053,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 2), 1, &OpDispatchBuilder::RCLSmallerOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 3), 1, &OpDispatchBuilder::RCRSmallerOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 4), 1, &OpDispatchBuilder::SHLOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR @@ -6083,7 +6062,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 2), 1, &OpDispatchBuilder::RCLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 3), 1, &OpDispatchBuilder::RCROp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 4), 1, &OpDispatchBuilder::SHLOp}, - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 6d3126b38..194c5fc56 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -333,8 +333,8 @@ public: void SHLOp(OpcodeArgs); template void SHLImmediateOp(OpcodeArgs); - template void SHROp(OpcodeArgs); + template void SHRImmediateOp(OpcodeArgs); void SHLDOp(OpcodeArgs); void SHLDImmediateOp(OpcodeArgs); From a05cc06ab42ed133e69f126252a364322926d889 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 3 Apr 2024 13:36:31 -0400 Subject: [PATCH 09/10] OpcodeDispatcher: unify imm/1-bit ASHR Signed-off-by: Alyssa Rosenzweig --- .../Interface/Core/OpcodeDispatcher.cpp | 42 +++++-------------- .../Source/Interface/Core/OpcodeDispatcher.h | 2 +- 2 files changed, 12 insertions(+), 32 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 2ed6176f1..e0ead2bfc 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -1771,19 +1771,11 @@ void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) { } } -template void OpDispatchBuilder::ASHROp(OpcodeArgs) { - OrderedNode *Src; - OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); + auto Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); + auto Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags); const auto Size = GetSrcBitSize(Op); - - if constexpr (SHR1Bit) { - Src = _Constant(Size, 1); - } else { - Src = LoadSource(GPRClass, Op, Op->Src[1], Op->Flags); - } - if (Size < 32) { Dest = _Sbfe(OpSize::i64Bit, Size, 0, Dest); } @@ -1791,28 +1783,16 @@ void OpDispatchBuilder::ASHROp(OpcodeArgs) { OrderedNode *Result = _Ashr(IR::SizeToOpSize(std::max(4, GetSrcSize(Op))), Dest, Src); StoreResult(GPRClass, Op, Result, -1); - if constexpr (SHR1Bit) { - GenerateFlags_SignShiftRightImmediate(Op, Result, Dest, 1); - } else { - GenerateFlags_SignShiftRight(Op, Result, Dest, Src); - } + GenerateFlags_SignShiftRight(Op, Result, Dest, Src); } +template void OpDispatchBuilder::ASHRImmediateOp(OpcodeArgs) { OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags); - LOGMAN_THROW_A_FMT(Op->Src[1].IsLiteral(), "Src1 needs to be literal here"); - - uint64_t Shift = Op->Src[1].Data.Literal.Value; + uint64_t Shift = LoadConstantShift(Op, SHR1Bit); const auto Size = GetSrcBitSize(Op); - // x86 masks the shift by 0x3F or 0x1F depending on size of op - if (Size == 64) { - Shift &= 0x3F; - } else { - Shift &= 0x1F; - } - if (Size < 32) { Dest = _Sbfe(OpSize::i64Bit, Size, 0, Dest); } @@ -6019,7 +5999,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC0), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 1), 1, &OpDispatchBuilder::RotateOp}, @@ -6028,7 +6008,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xC1), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 1), 1, &OpDispatchBuilder::RotateOp}, @@ -6037,7 +6017,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, // 1Bit SHR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD0), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 1), 1, &OpDispatchBuilder::RotateOp}, @@ -6046,7 +6026,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 4), 1, &OpDispatchBuilder::SHLImmediateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 5), 1, &OpDispatchBuilder::SHRImmediateOp}, // 1Bit SHR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 6), 1, &OpDispatchBuilder::SHLImmediateOp}, // SAL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD1), 7), 1, &OpDispatchBuilder::ASHRImmediateOp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 1), 1, &OpDispatchBuilder::RotateOp}, @@ -6055,7 +6035,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 4), 1, &OpDispatchBuilder::SHLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD2), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 0), 1, &OpDispatchBuilder::RotateOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 1), 1, &OpDispatchBuilder::RotateOp}, @@ -6064,7 +6044,7 @@ void InstallOpcodeHandlers(Context::OperatingMode Mode) { {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 4), 1, &OpDispatchBuilder::SHLOp}, {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 5), 1, &OpDispatchBuilder::SHROp}, // SHR by CL {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 6), 1, &OpDispatchBuilder::SHLOp}, // SAL - {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR + {OPD(FEXCore::X86Tables::TYPE_GROUP_2, OpToIndex(0xD3), 7), 1, &OpDispatchBuilder::ASHROp}, // SAR // GROUP 3 {OPD(FEXCore::X86Tables::TYPE_GROUP_3, OpToIndex(0xF6), 0), 1, &OpDispatchBuilder::TESTOp<1>}, diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 194c5fc56..f43383dd2 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -340,8 +340,8 @@ public: void SHLDImmediateOp(OpcodeArgs); void SHRDOp(OpcodeArgs); void SHRDImmediateOp(OpcodeArgs); - template void ASHROp(OpcodeArgs); + template void ASHRImmediateOp(OpcodeArgs); template void RotateOp(OpcodeArgs); From a787daae412f6296e5dd5cd01e1d1f8e0f7b048b Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 4 Apr 2024 07:42:27 -0400 Subject: [PATCH 10/10] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- .../FlagM/PrimaryGroup.json | 24 ++++++++----------- .../InstructionCountCI/PrimaryGroup.json | 24 ++++++++----------- 2 files changed, 20 insertions(+), 28 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index c5c83bc75..1bed89c1e 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -1295,13 +1295,12 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsl w21, w20, #1", - "bfxil x4, x21, #0, #8", - "uxtb w26, w21", + "lsl w26, w20, #1", + "bfxil x4, x26, #0, #8", "cmn wzr, w26, lsl #24", "rmif x20, #6, #nzCv", "eor w20, w26, w20", @@ -1326,7 +1325,7 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "sxtb x20, w20", - "asr w26, w20, #1", + "asr x26, x20, #1", "bfxil x4, x26, #0, #8", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv" @@ -1471,13 +1470,12 @@ ] }, "shl ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsl w21, w20, #1", - "bfxil x4, x21, #0, #16", - "uxth w26, w21", + "lsl w26, w20, #1", + "bfxil x4, x26, #0, #16", "cmn wzr, w26, lsl #16", "rmif x20, #14, #nzCv", "eor w20, w26, w20", @@ -1552,7 +1550,7 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "sxth x20, w20", - "asr w26, w20, #1", + "asr x26, x20, #1", "bfxil x4, x26, #0, #16", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv" @@ -1671,14 +1669,13 @@ ] }, "shl al, cl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd2 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", "uxtb w21, w5", "lsl w22, w20, w21", "bfxil x4, x22, #0, #8", - "uxtb w22, w22", "cbz x21, #+0x24", "cmn wzr, w22, lsl #24", "mov w23, #0x8", @@ -1939,14 +1936,13 @@ ] }, "shl ax, cl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "uxth w20, w4", "uxth w21, w5", "lsl w22, w20, w21", "bfxil x4, x22, #0, #16", - "uxth w22, w22", "cbz x21, #+0x24", "cmn wzr, w22, lsl #16", "mov w23, #0x10", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 1bb30c827..e17cc5312 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -1504,13 +1504,12 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", - "lsl w21, w20, #1", - "bfxil x4, x21, #0, #8", - "uxtb w26, w21", + "lsl w26, w20, #1", + "bfxil x4, x26, #0, #8", "cmn wzr, w26, lsl #24", "ubfx x21, x20, #7, #1", "mrs x22, nzcv", @@ -1543,7 +1542,7 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "sxtb x20, w20", - "asr w26, w20, #1", + "asr x26, x20, #1", "bfxil x4, x26, #0, #8", "cmn wzr, w26, lsl #24", "ubfx x20, x20, #0, #1", @@ -1769,13 +1768,12 @@ ] }, "shl ax, 1": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "uxth w20, w4", - "lsl w21, w20, #1", - "bfxil x4, x21, #0, #16", - "uxth w26, w21", + "lsl w26, w20, #1", + "bfxil x4, x26, #0, #16", "cmn wzr, w26, lsl #16", "ubfx x21, x20, #15, #1", "mrs x22, nzcv", @@ -1874,7 +1872,7 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "sxth x20, w20", - "asr w26, w20, #1", + "asr x26, x20, #1", "bfxil x4, x26, #0, #16", "cmn wzr, w26, lsl #16", "ubfx x20, x20, #0, #1", @@ -2026,14 +2024,13 @@ ] }, "shl al, cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": "GROUP2 0xd2 /4", "ExpectedArm64ASM": [ "uxtb w20, w4", "uxtb w21, w5", "lsl w22, w20, w21", "bfxil x4, x22, #0, #8", - "uxtb w22, w22", "cbz x21, #+0x34", "cmn wzr, w22, lsl #24", "mov w23, #0x8", @@ -2381,14 +2378,13 @@ ] }, "shl ax, cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 17, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "uxth w20, w4", "uxth w21, w5", "lsl w22, w20, w21", "bfxil x4, x22, #0, #16", - "uxth w22, w22", "cbz x21, #+0x34", "cmn wzr, w22, lsl #16", "mov w23, #0x10",