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OpcodeDispatcher: Handle VRSQRTSS

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This commit is contained in:
lioncash 2022-12-12 16:13:43 +00:00
parent 3504ba068e
commit c4c93f5bfe
5 changed files with 85 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5832,6 +5832,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b11, 0x51), 1, &OpDispatchBuilder::AVXVectorUnaryOp<IR::OP_VFSQRT, 8, true>},
{OPD(1, 0b00, 0x52), 1, &OpDispatchBuilder::AVXVectorUnaryOp<IR::OP_VFRSQRT, 4, false>},
{OPD(1, 0b10, 0x52), 1, &OpDispatchBuilder::AVXVectorUnaryOp<IR::OP_VFRSQRT, 4, true>},
{OPD(1, 0b00, 0x54), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>},
{OPD(1, 0b01, 0x54), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>},

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
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@ -627,6 +627,8 @@ template
void OpDispatchBuilder::AVXVectorUnaryOp<IR::OP_VFSQRT, 8, true>(OpcodeArgs);
template
void OpDispatchBuilder::AVXVectorUnaryOp<IR::OP_VFRSQRT, 4, false>(OpcodeArgs);
template
void OpDispatchBuilder::AVXVectorUnaryOp<IR::OP_VFRSQRT, 4, true>(OpcodeArgs);
template<FEXCore::IR::IROps IROp, size_t ElementSize>
void OpDispatchBuilder::VectorUnaryDuplicateOp(OpcodeArgs) {

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -57,7 +57,7 @@ void InitializeVEXTables() {
{OPD(1, 0b11, 0x51), 1, X86InstInfo{"VSQRTSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b00, 0x52), 1, X86InstInfo{"VRSQRTPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b10, 0x52), 1, X86InstInfo{"VRSQRTSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b10, 0x52), 1, X86InstInfo{"VRSQRTSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b00, 0x53), 1, X86InstInfo{"VRCPPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b10, 0x53), 1, X86InstInfo{"VRCPSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

1
unittests/ASM/Disabled_Tests
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@ -3,6 +3,7 @@ Test_REP/F3_52.asm
Test_REP/F3_53.asm
Test_TwoByte/0F_52.asm
Test_TwoByte/0F_53.asm
Test_VEX/vrsqrtss.asm
Test_VEX/vrsqrtps.asm
# Not supported in userspace in all cases

80
unittests/ASM/VEX/vrsqrtss.asm Normal file
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@ -0,0 +1,80 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x414243443F800000", "0xEEEEEEEEEEEEEEEE", "0x0000000000000000", "0x0000000000000000"],
"XMM1": ["0x414243443F000000", "0xDDDDDDDDDDDDDDDD", "0x0000000000000000", "0x0000000000000000"],
"XMM2": ["0x414243443EAAAAAB", "0xCCCCCCCCCCCCCCCC", "0x0000000000000000", "0x0000000000000000"],
"XMM3": ["0x414243443E800000", "0xBBBBBBBBBBBBBBBB", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x414243443F800000", "0xAAAAAAAAAAAAAAAA", "0x0000000000000000", "0x0000000000000000"],
"XMM5": ["0x414243443F000000", "0xAAAAAAAAAAAAAAAA", "0x0000000000000000", "0x0000000000000000"],
"XMM6": ["0x414243443EAAAAAB", "0xAAAAAAAAAAAAAAAA", "0x0000000000000000", "0x0000000000000000"],
"XMM7": ["0x414243443E800000", "0xAAAAAAAAAAAAAAAA", "0x0000000000000000", "0x0000000000000000"],
"XMM8": ["0x414243443F800000", "0xDDDDDDDDDDDDDDDD", "0x0000000000000000", "0x0000000000000000"],
"XMM9": ["0x414243443F000000", "0xCCCCCCCCCCCCCCCC", "0x0000000000000000", "0x0000000000000000"],
"XMM10": ["0x414243443EAAAAAB", "0xBBBBBBBBBBBBBBBB", "0x0000000000000000", "0x0000000000000000"],
"XMM11": ["0x414243443E800000", "0xAAAAAAAAAAAAAAAA", "0x0000000000000000", "0x0000000000000000"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
vmovapd ymm0, [rdx + 32 * 0]
vmovapd ymm1, [rdx + 32 * 1]
vmovapd ymm2, [rdx + 32 * 2]
vmovapd ymm3, [rdx + 32 * 3]
vmovapd ymm4, [rdx + 32 * 4]
vmovapd ymm5, [rdx + 32 * 4]
vmovapd ymm6, [rdx + 32 * 4]
vmovapd ymm7, [rdx + 32 * 4]
; Same register
vrsqrtss xmm0, xmm0, xmm0
vrsqrtss xmm1, xmm1, xmm1
vrsqrtss xmm2, xmm2, xmm2
vrsqrtss xmm3, xmm3, xmm3
; Memory operand
vrsqrtss xmm4, xmm4, [rdx + 32 * 0]
vrsqrtss xmm5, xmm5, [rdx + 32 * 1]
vrsqrtss xmm6, xmm6, [rdx + 32 * 2]
vrsqrtss xmm7, xmm7, [rdx + 32 * 3]
; Memory operand different source register
vrsqrtss xmm8, xmm1, [rdx + 32 * 0]
vrsqrtss xmm9, xmm2, [rdx + 32 * 1]
vrsqrtss xmm10, xmm3, [rdx + 32 * 2]
vrsqrtss xmm11, xmm4, [rdx + 32 * 3]
hlt
align 32
.data:
dq 0x414243443F800000 ; 1.0
dq 0xEEEEEEEEEEEEEEEE
dq 0x5152535455565758
dq 0x5152535455565758
dq 0x4142434440800000 ; 4.0
dq 0xDDDDDDDDDDDDDDDD
dq 0x5152535455565758
dq 0x5152535455565758
dq 0x4142434441100000 ; 9.0
dq 0xCCCCCCCCCCCCCCCC
dq 0x5152535455565758
dq 0x5152535455565758
dq 0x4142434441800000 ; 16.0
dq 0xBBBBBBBBBBBBBBBB
dq 0x5152535455565758
dq 0x5152535455565758
dq 0x4142434441C80000 ; 25.0
dq 0xAAAAAAAAAAAAAAAA
dq 0x5152535455565758
dq 0x5152535455565758