mirror of
https://github.com/FEX-Emu/FEX.git
synced 2024-12-13 17:15:41 +00:00
Fixes a bunch of various bugs in the x86 translation
Removes a bunch of MMX instructions accidently exposed in the opdispatcher tables.
This commit is contained in:
Ryan Houdek
Stefanos Kornilios Mitsis Poiitidis
parent
c721810516
commit
cd5e34e8cc
@ -1158,13 +1158,7 @@ void OpDispatchBuilder::SHLDOp(OpcodeArgs) {
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OrderedNode *Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Shift{};
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if (Op->OP == 0xA4) {
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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Shift = _Constant(Op->Src[1].TypeLiteral.Literal);
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}
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else
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Shift = _LoadContext(1, offsetof(FEXCore::Core::CPUState, gregs[FEXCore::X86State::REG_RCX]), GPRClass);
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OrderedNode *Shift = LoadSource_WithOpSize(GPRClass, Op, Op->Src[1], 1, Op->Flags, -1);
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auto Size = GetSrcSize(Op) * 8;
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@ -1174,7 +1168,7 @@ void OpDispatchBuilder::SHLDOp(OpcodeArgs) {
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else
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Shift = _And(Shift, _Constant(0x1F));
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auto ShiftRight = _Neg(Shift);
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auto ShiftRight = _Sub(_Constant(Size), Shift);
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OrderedNode *Res{};
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if (Size == 16) {
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@ -1370,18 +1364,13 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) {
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uint32_t Size = GetSrcSize(Op);
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uint32_t Mask = Size * 8 - 1;
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OrderedNode *SizeMask = _Constant(Mask);
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OrderedNode *AddressShift = _Constant(32 - __builtin_clz(Mask));
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// Get the bit selection from the src
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OrderedNode *BitSelect = _And(Src, SizeMask);
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// First shift out the selection bits
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Src = _Lshr(Src, AddressShift);
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// Now multiply by operand size to get correct indexing
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if (Size != 1) {
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Src = _Lshl(Src, _Constant(Size - 1));
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}
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// Address is provided as bits we want BYTE offsets
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// Just shift by 3 to get the offset
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Src = _Lshr(Src, _Constant(3));
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// Get the address offset by shifting out the size of the op (To shift out the bit selection)
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// Then use that to index in to the memory location by size of op
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@ -1422,18 +1411,13 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
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uint32_t Size = GetSrcSize(Op);
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uint32_t Mask = Size * 8 - 1;
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OrderedNode *SizeMask = _Constant(Mask);
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OrderedNode *AddressShift = _Constant(32 - __builtin_clz(Mask));
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// Get the bit selection from the src
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OrderedNode *BitSelect = _And(Src, SizeMask);
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// First shift out the selection bits
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Src = _Lshr(Src, AddressShift);
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// Now multiply by operand size to get correct indexing
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if (Size != 1) {
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Src = _Lshl(Src, _Constant(Size - 1));
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}
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// Address is provided as bits we want BYTE offsets
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// Just shift by 3 to get the offset
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Src = _Lshr(Src, _Constant(3));
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// Get the address offset by shifting out the size of the op (To shift out the bit selection)
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// Then use that to index in to the memory location by size of op
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@ -1477,18 +1461,13 @@ void OpDispatchBuilder::BTSOp(OpcodeArgs) {
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uint32_t Size = GetSrcSize(Op);
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uint32_t Mask = Size * 8 - 1;
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OrderedNode *SizeMask = _Constant(Mask);
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OrderedNode *AddressShift = _Constant(32 - __builtin_clz(Mask));
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// Get the bit selection from the src
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OrderedNode *BitSelect = _And(Src, SizeMask);
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// First shift out the selection bits
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Src = _Lshr(Src, AddressShift);
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// Now multiply by operand size to get correct indexing
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if (Size != 1) {
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Src = _Lshl(Src, _Constant(Size - 1));
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}
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// Address is provided as bits we want BYTE offsets
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// Just shift by 3 to get the offset
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Src = _Lshr(Src, _Constant(3));
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// Get the address offset by shifting out the size of the op (To shift out the bit selection)
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// Then use that to index in to the memory location by size of op
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@ -2296,7 +2275,7 @@ void OpDispatchBuilder::MOVLPOp(OpcodeArgs) {
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StoreResult(FPRClass, Op, Result, -1);
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}
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else {
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StoreResult(FPRClass, Op, Src, 8);
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StoreResult_WithOpSize(FPRClass, Op, Op->Dest, Src, 8, 8);
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}
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}
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@ -2323,16 +2302,9 @@ void OpDispatchBuilder::MOVSDOp(OpcodeArgs) {
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}
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PADDQOp(OpcodeArgs) {
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auto Size = GetSrcSize(Op);
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uint8_t ElementSize = 8;
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switch (Op->OP) {
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case 0xD4: ElementSize = 8; break;
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case 0xFC: ElementSize = 1; break;
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case 0xFD: ElementSize = 2; break;
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case 0xFE: ElementSize = 4; break;
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default: LogMan::Msg::A("Unknown PADD op: 0x%04x", Op->OP); break;
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}
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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@ -2341,16 +2313,9 @@ void OpDispatchBuilder::PADDQOp(OpcodeArgs) {
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StoreResult(FPRClass, Op, ALUOp, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PSUBQOp(OpcodeArgs) {
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auto Size = GetSrcSize(Op);
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uint8_t ElementSize = 8;
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switch (Op->OP) {
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case 0xF8: ElementSize = 1; break;
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case 0xF9: ElementSize = 2; break;
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case 0xFA: ElementSize = 4; break;
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case 0xFB: ElementSize = 8; break;
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default: LogMan::Msg::A("Unknown PSUB op: 0x%04x", Op->OP); break;
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}
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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@ -2601,15 +2566,9 @@ void OpDispatchBuilder::PINSROp(OpcodeArgs) {
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StoreResult(FPRClass, Op, ALUOp, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PCMPEQOp(OpcodeArgs) {
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auto Size = GetSrcSize(Op);
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uint8_t ElementSize = 4;
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switch (Op->OP) {
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case 0x74: ElementSize = 1; break;
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case 0x75: ElementSize = 2; break;
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case 0x76: ElementSize = 4; break;
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default: LogMan::Msg::A("Unknown ElementSize"); break;
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}
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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@ -3806,6 +3765,33 @@ void OpDispatchBuilder::PSRLD(OpcodeArgs) {
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StoreResult(FPRClass, Op, Shift, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PSRLI(OpcodeArgs) {
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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uint64_t ShiftConstant = Op->Src[1].TypeLiteral.Literal;
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auto Size = GetSrcSize(Op);
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auto Shift = _VUShrI(Size, ElementSize, Dest, ShiftConstant);
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StoreResult(FPRClass, Op, Shift, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PSLLI(OpcodeArgs) {
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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uint64_t ShiftConstant = Op->Src[1].TypeLiteral.Literal;
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auto Size = GetSrcSize(Op);
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auto Shift = _VShlI(Size, ElementSize, Dest, ShiftConstant);
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StoreResult(FPRClass, Op, Shift, -1);
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}
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template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
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void OpDispatchBuilder::PSLL(OpcodeArgs) {
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[SrcIndex], Op->Flags, -1);
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@ -3849,19 +3835,6 @@ void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
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StoreResult(FPRClass, Op, Result, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PSRAOp(OpcodeArgs) {
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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OrderedNode *Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags, -1);
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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auto Size = GetDstSize(Op);
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auto Result = _VSShrS(Size, ElementSize, Dest, Src);
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StoreResult(FPRClass, Op, Result, -1);
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}
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template<size_t ElementSize>
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void OpDispatchBuilder::PSRAIOp(OpcodeArgs) {
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LogMan::Throw::A(Op->Src[1].TypeNone.Type == FEXCore::X86Tables::DecodedOperand::TYPE_LITERAL, "Src1 needs to be literal here");
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@ -3877,7 +3850,7 @@ void OpDispatchBuilder::PSRAIOp(OpcodeArgs) {
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void OpDispatchBuilder::MOVDDUPOp(OpcodeArgs) {
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OrderedNode *Src = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags, -1);
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OrderedNode *Res = _CreateVector2(Src, Src);
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OrderedNode *Res = _SplatVector2(Src);
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StoreResult(FPRClass, Op, Res, -1);
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}
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@ -4434,12 +4407,12 @@ void InstallOpcodeHandlers() {
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{0x38, 6, &OpDispatchBuilder::CMPOp<0>},
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{0x50, 8, &OpDispatchBuilder::PUSHOp},
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{0x58, 8, &OpDispatchBuilder::POPOp},
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{0x68, 1, &OpDispatchBuilder::PUSHOp},
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{0x6A, 1, &OpDispatchBuilder::PUSHOp},
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{0x63, 1, &OpDispatchBuilder::MOVSXDOp},
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{0x68, 1, &OpDispatchBuilder::PUSHOp},
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{0x69, 1, &OpDispatchBuilder::IMUL2SrcOp},
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{0x6A, 1, &OpDispatchBuilder::PUSHOp},
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{0x6B, 1, &OpDispatchBuilder::IMUL2SrcOp},
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{0x70, 16, &OpDispatchBuilder::CondJUMPOp},
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{0x84, 2, &OpDispatchBuilder::TESTOp<0>},
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{0x86, 2, &OpDispatchBuilder::XCHGOp},
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@ -4462,7 +4435,7 @@ void InstallOpcodeHandlers() {
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{0xB0, 16, &OpDispatchBuilder::MOVGPROp<0>},
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{0xC2, 2, &OpDispatchBuilder::RETOp},
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{0xC9, 1, &OpDispatchBuilder::LEAVEOp},
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{0xCC, 3, &OpDispatchBuilder::INTOp},
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{0xCC, 2, &OpDispatchBuilder::INTOp},
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{0xE8, 1, &OpDispatchBuilder::CALLOp},
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{0xE9, 1, &OpDispatchBuilder::JUMPOp},
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{0xEB, 1, &OpDispatchBuilder::JUMPOp},
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@ -4530,42 +4503,17 @@ void InstallOpcodeHandlers() {
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{0x5D, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFMIN, 4>},
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{0x5E, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFDIV, 4>},
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{0x5F, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VFMAX, 4>},
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{0x60, 1, &OpDispatchBuilder::PUNPCKLOp<1>},
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{0x61, 1, &OpDispatchBuilder::PUNPCKLOp<2>},
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{0x62, 1, &OpDispatchBuilder::PUNPCKLOp<4>},
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{0x64, 1, &OpDispatchBuilder::PCMPGTOp<1>},
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{0x65, 1, &OpDispatchBuilder::PCMPGTOp<2>},
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{0x66, 1, &OpDispatchBuilder::PCMPGTOp<4>},
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{0x68, 3, &OpDispatchBuilder::UnhandledOp},
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{0x6C, 1, &OpDispatchBuilder::UnhandledOp},
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{0x71, 1, nullptr}, // GROUP 12
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{0x72, 1, nullptr}, // GROUP 13
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{0x73, 1, nullptr}, // GROUP 14
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{0x74, 3, &OpDispatchBuilder::PCMPEQOp},
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{0xAE, 1, nullptr}, // GROUP 15
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{0xB9, 1, nullptr}, // GROUP 10
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{0xBA, 1, nullptr}, // GROUP 8
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{0xC2, 1, &OpDispatchBuilder::VFCMPOp<4, false>},
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{0xC4, 1, &OpDispatchBuilder::PINSROp<4>},
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{0xC6, 1, &OpDispatchBuilder::SHUFOp<4>},
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{0xC7, 1, nullptr}, // GROUP 9
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{0xD4, 1, &OpDispatchBuilder::PADDQOp},
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{0xD6, 1, &OpDispatchBuilder::MOVQOp},
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{0xD7, 1, &OpDispatchBuilder::MOVMSKOp<1>},
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// XXX: Untested
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{0xDA, 1, &OpDispatchBuilder::PMINUOp<1>},
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{0xDE, 1, &OpDispatchBuilder::PMAXUOp<1>},
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{0xDF, 1, &OpDispatchBuilder::ANDNOp},
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{0xEA, 1, &OpDispatchBuilder::PMINSWOp},
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{0xEB, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 8>},
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{0xEF, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 8>},
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{0xF8, 4, &OpDispatchBuilder::PSUBQOp},
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{0xFD, 1, &OpDispatchBuilder::PADDQOp},
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{0xFE, 1, &OpDispatchBuilder::PADDQOp},
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};
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#define OPD(group, prefix, Reg) (((group - FEXCore::X86Tables::TYPE_GROUP_1) << 6) | (prefix) << 3 | (Reg))
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@ -4701,11 +4649,11 @@ void InstallOpcodeHandlers() {
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{0x19, 7, &OpDispatchBuilder::NOPOp},
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{0x2A, 1, &OpDispatchBuilder::CVT<8, true>},
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{0x2C, 1, &OpDispatchBuilder::FCVT<8, true>},
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{0x5A, 1, &OpDispatchBuilder::FCVTF<4, 8>},
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{0x51, 1, &OpDispatchBuilder::VectorUnaryOp<IR::OP_VFSQRT, 8, true>},
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//x52 = Invalid
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{0x58, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFADD, 8>},
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{0x59, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMUL, 8>},
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{0x5A, 1, &OpDispatchBuilder::FCVTF<4, 8>},
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{0x5C, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFSUB, 8>},
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{0x5D, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFMIN, 8>},
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{0x5E, 1, &OpDispatchBuilder::VectorScalarALUOp<IR::OP_VFDIV, 8>},
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@ -4754,7 +4702,9 @@ void InstallOpcodeHandlers() {
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{0x70, 1, &OpDispatchBuilder::PSHUFDOp<4, true>},
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// XXX: Causing IR interpreter some problems
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{0x74, 3, &OpDispatchBuilder::PCMPEQOp},
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{0x74, 1, &OpDispatchBuilder::PCMPEQOp<1>},
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{0x75, 1, &OpDispatchBuilder::PCMPEQOp<2>},
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{0x76, 1, &OpDispatchBuilder::PCMPEQOp<4>},
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{0x78, 1, nullptr}, // GROUP 17
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{0x7E, 1, &OpDispatchBuilder::MOVDOp},
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{0x7F, 1, &OpDispatchBuilder::MOVUPSOp},
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@ -4762,7 +4712,7 @@ void InstallOpcodeHandlers() {
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{0xC4, 1, &OpDispatchBuilder::PINSROp<4>},
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{0xC6, 1, &OpDispatchBuilder::SHUFOp<8>},
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{0xD4, 1, &OpDispatchBuilder::PADDQOp},
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{0xD4, 1, &OpDispatchBuilder::PADDQOp<8>},
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// XXX: Causes LLVM to crash if commented out?
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{0xD6, 1, &OpDispatchBuilder::MOVQOp},
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{0xD7, 1, &OpDispatchBuilder::MOVMSKOp<1>}, // PMOVMSKB
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@ -4775,16 +4725,21 @@ void InstallOpcodeHandlers() {
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{0xE2, 1, &OpDispatchBuilder::PSRAIOp<4>},
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{0xE7, 1, &OpDispatchBuilder::MOVVectorOp},
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{0xEA, 1, &OpDispatchBuilder::PMINSWOp},
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{0xEB, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VOR, 16>},
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{0xEC, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VQADD, 1>},
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{0xED, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VQADD, 2>},
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{0xEE, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VSMAX, 2>},
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{0xEF, 1, &OpDispatchBuilder::VectorALUOp<IR::OP_VXOR, 16>},
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{0xF2, 1, &OpDispatchBuilder::PSLL<4, true, 0>},
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{0xF3, 1, &OpDispatchBuilder::PSLL<8, true, 0>},
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{0xF4, 1, &OpDispatchBuilder::PMULOp<4, false>},
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{0xF8, 4, &OpDispatchBuilder::PSUBQOp},
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{0xFD, 1, &OpDispatchBuilder::PADDQOp},
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{0xFE, 1, &OpDispatchBuilder::PADDQOp},
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{0xF8, 1, &OpDispatchBuilder::PSUBQOp<1>},
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{0xF9, 1, &OpDispatchBuilder::PSUBQOp<2>},
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{0xFA, 1, &OpDispatchBuilder::PSUBQOp<4>},
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{0xFB, 1, &OpDispatchBuilder::PSUBQOp<8>},
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{0xFD, 1, &OpDispatchBuilder::PADDQOp<2>},
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{0xFE, 1, &OpDispatchBuilder::PADDQOp<4>},
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};
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constexpr uint16_t PF_NONE = 0;
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@ -4815,24 +4770,19 @@ constexpr uint16_t PF_F2 = 3;
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{OPD(FEXCore::X86Tables::TYPE_GROUP_8, PF_F2, 7), 1, &OpDispatchBuilder::BTCOp<1>},
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// GROUP 12
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{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAOp<2>},
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{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 4), 1, &OpDispatchBuilder::PSRAOp<2>},
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{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 2), 1, &OpDispatchBuilder::PSRLI<2>},
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{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 4), 1, &OpDispatchBuilder::PSRAIOp<2>},
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{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_66, 6), 1, &OpDispatchBuilder::PSLLI<2>},
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// GROUP 13
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{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLD<4, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAOp<4>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_NONE, 6), 1, &OpDispatchBuilder::PSLL<4, true, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 2), 1, &OpDispatchBuilder::PSRLD<4, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 4), 1, &OpDispatchBuilder::PSRAOp<4>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 6), 1, &OpDispatchBuilder::PSLL<4, true, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 2), 1, &OpDispatchBuilder::PSRLI<4>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 4), 1, &OpDispatchBuilder::PSRAIOp<4>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_13, PF_66, 6), 1, &OpDispatchBuilder::PSLLI<4>},
|
||||
|
||||
// GROUP 14
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLD<8, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_NONE, 6), 1, &OpDispatchBuilder::PSLL<8, true, 1>},
|
||||
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 2), 1, &OpDispatchBuilder::PSRLD<8, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 6), 1, &OpDispatchBuilder::PSLL<8, true, 1>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 2), 1, &OpDispatchBuilder::PSRLI<8>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 3), 1, &OpDispatchBuilder::PSRLDQ},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 6), 1, &OpDispatchBuilder::PSLLI<8>},
|
||||
{OPD(FEXCore::X86Tables::TYPE_GROUP_14, PF_66, 7), 1, &OpDispatchBuilder::PSLLDQ},
|
||||
|
||||
// GROUP 15
|
||||
|
||||
@ -193,7 +193,9 @@ public:
|
||||
template<FEXCore::IR::IROps IROp, size_t ElementSize, bool Scalar>
|
||||
void VectorUnaryOp(OpcodeArgs);
|
||||
void MOVQOp(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PADDQOp(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PSUBQOp(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PMINUOp(OpcodeArgs);
|
||||
@ -208,19 +210,22 @@ public:
|
||||
void PUNPCKHOp(OpcodeArgs);
|
||||
template<size_t ElementSize, bool Low>
|
||||
void PSHUFDOp(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PCMPEQOp(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PCMPGTOp(OpcodeArgs);
|
||||
void MOVDOp(OpcodeArgs);
|
||||
template<size_t ElementSize, uint32_t SrcIndex>
|
||||
void PSRLD(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PSRLI(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PSLLI(OpcodeArgs);
|
||||
template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
|
||||
void PSLL(OpcodeArgs);
|
||||
void PSRLDQ(OpcodeArgs);
|
||||
void PSLLDQ(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PSRAOp(OpcodeArgs);
|
||||
template<size_t ElementSize>
|
||||
void PSRAIOp(OpcodeArgs);
|
||||
void MOVDDUPOp(OpcodeArgs);
|
||||
template<size_t DstElementSize, bool Signed>
|
||||
|
||||
@ -335,7 +335,7 @@ void InitializeSecondaryTables() {
|
||||
|
||||
{0x10, 1, X86InstInfo{"MOVSD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x11, 1, X86InstInfo{"MOVSD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x12, 1, X86InstInfo{"MOVDDUP", TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | GenFlagsSrcSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x12, 1, X86InstInfo{"MOVDDUP", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x13, 6, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
|
||||
{0x19, 7, X86InstInfo{"", TYPE_COPY_OTHER, FLAGS_NONE, 0, nullptr}},
|
||||
|
||||
@ -408,8 +408,8 @@ void InitializeSecondaryTables() {
|
||||
|
||||
{0x10, 1, X86InstInfo{"MOVUPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x11, 1, X86InstInfo{"MOVUPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x12, 1, X86InstInfo{"MOVLPD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x13, 1, X86InstInfo{"MOVLPD", TYPE_INST, GenFlagsSameSize(SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x12, 1, X86InstInfo{"MOVLPD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x13, 1, X86InstInfo{"MOVLPD", TYPE_INST, GenFlagsSizes(SIZE_64BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x14, 1, X86InstInfo{"UNPCKLPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x15, 1, X86InstInfo{"UNPCKHPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
{0x16, 1, X86InstInfo{"MOVHPD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_SF_MOD_MEM_ONLY | FLAGS_XMM_FLAGS, 0, nullptr}},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user