mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-02-11 01:46:19 +00:00
Arm64: Work with more unaligned atomic operations
The latest ARMv8.0 toolchain is implementing fetch_add with a bic rather than an and. Not sure why they started doing this but support the remaining logical operations in our unaligned atomics handler. Fixes the Interpreter ARMv8.0 atomic ops. Fixes #1742
This commit is contained in:
Ryan Houdek
parent
3bbff8a948
commit
d23c76d0a9
@ -513,7 +513,8 @@ uint64_t HandleCASPAL_ARMv8(void *_ucontext, void *_info, uint32_t Instr) {
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//Only 32-bit pairs
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for(int i = 1; i < 10; i++) {
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uint32_t NextInstr = PC[i];
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if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_INST) {
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if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_INST ||
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(NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_SHIFT_INST) {
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ExpectedReg1 = GetRmReg(NextInstr);
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} else if ((NextInstr & FEXCore::ArchHelpers::Arm64::CCMP_MASK) == FEXCore::ArchHelpers::Arm64::CCMP_INST) {
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ExpectedReg2 = GetRmReg(NextInstr);
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@ -1745,7 +1746,8 @@ static uint64_t HandleCAS_NoAtomics(void *_ucontext, void *_info)
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#endif
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DesiredReg = GetRdReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_INST) {
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_INST ||
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(NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_SHIFT_INST) {
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ExpectedReg = GetRmReg(NextInstr);
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}
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}
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@ -1828,11 +1830,13 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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// Scan forward at most five instructions to find our instructions
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for (size_t i = 1; i < 6; ++i) {
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uint32_t NextInstr = PC[i];
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if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::ADD_INST) {
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if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::ADD_INST ||
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(NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::ADD_SHIFT_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_ADD;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::SUB_INST) {
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::SUB_INST ||
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(NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::SUB_SHIFT_INST) {
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uint32_t RnReg = GetRnReg(NextInstr);
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if (RnReg == REGISTER_MASK) {
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// Zero reg means neg
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@ -1843,21 +1847,34 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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}
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_INST) {
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return HandleCAS_NoAtomics(_ucontext, _info); //ARMv8.0 CAS
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_INST ||
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(NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::CMP_SHIFT_INST ) {
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return HandleCAS_NoAtomics(_ucontext, _info); //ARMv8.0 CAS
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::AND_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_AND;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::BIC_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_BIC;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::OR_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_OR;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::ORN_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_ORN;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::EOR_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_EOR;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::ALU_OP_MASK) == FEXCore::ArchHelpers::Arm64::EON_INST) {
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AtomicOp = ExclusiveAtomicPairType::TYPE_EON;
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DataSourceReg = GetRmReg(NextInstr);
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}
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else if ((NextInstr & FEXCore::ArchHelpers::Arm64::STLXR_MASK) == FEXCore::ArchHelpers::Arm64::STLXR_INST) {
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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// Just double check that the memory destination matches
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@ -1888,40 +1905,53 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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uint32_t Size = 1 << (Instr >> 30);
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constexpr bool DoRetry = true;
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auto NOPExpected = []<typename AtomicType>(AtomicType SrcVal, AtomicType) -> AtomicType {
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return SrcVal;
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};
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auto ADDDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal + Desired;
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};
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auto SUBDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal - Desired;
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};
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auto ANDDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal & Desired;
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};
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auto BICDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal & ~Desired;
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};
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auto ORDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal | Desired;
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};
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auto ORNDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal | ~Desired;
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};
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auto EORDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal ^ Desired;
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};
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auto EONDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal ^ ~Desired;
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};
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auto NEGDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return -SrcVal;
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};
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auto SWAPDesired = []<typename AtomicType>(AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return Desired;
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};
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if (Size == 2) {
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using AtomicType = uint16_t;
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auto NOPExpected = [](AtomicType SrcVal, AtomicType) -> AtomicType {
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return SrcVal;
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};
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auto ADDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal + Desired;
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};
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auto SUBDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal - Desired;
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};
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auto ANDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal & Desired;
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};
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auto ORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal | Desired;
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};
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auto EORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal ^ Desired;
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};
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auto NEGDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return -SrcVal;
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};
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auto SWAPDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return Desired;
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};
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CASDesiredFn<AtomicType> DesiredFunction{};
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switch (AtomicOp) {
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@ -1937,12 +1967,21 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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case ExclusiveAtomicPairType::TYPE_AND:
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DesiredFunction = ANDDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_BIC:
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DesiredFunction = BICDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_OR:
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DesiredFunction = ORDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_ORN:
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DesiredFunction = ORNDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_EOR:
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DesiredFunction = EORDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_EON:
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DesiredFunction = EONDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_NEG:
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DesiredFunction = NEGDesired;
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break;
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@ -1966,38 +2005,6 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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}
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else if (Size == 4) {
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using AtomicType = uint32_t;
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auto NOPExpected = [](AtomicType SrcVal, AtomicType) -> AtomicType {
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return SrcVal;
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};
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auto ADDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal + Desired;
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};
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auto SUBDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal - Desired;
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};
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auto ANDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal & Desired;
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};
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auto ORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal | Desired;
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};
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auto EORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal ^ Desired;
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};
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auto NEGDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return -SrcVal;
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};
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auto SWAPDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return Desired;
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};
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CASDesiredFn<AtomicType> DesiredFunction{};
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switch (AtomicOp) {
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@ -2013,12 +2020,21 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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case ExclusiveAtomicPairType::TYPE_AND:
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DesiredFunction = ANDDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_BIC:
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DesiredFunction = BICDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_OR:
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DesiredFunction = ORDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_ORN:
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DesiredFunction = ORNDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_EOR:
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DesiredFunction = EORDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_EON:
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DesiredFunction = EONDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_NEG:
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DesiredFunction = NEGDesired;
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break;
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@ -2042,38 +2058,6 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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}
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else if (Size == 8) {
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using AtomicType = uint64_t;
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auto NOPExpected = [](AtomicType SrcVal, AtomicType) -> AtomicType {
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return SrcVal;
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};
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auto ADDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal + Desired;
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};
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auto SUBDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal - Desired;
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};
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auto ANDDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal & Desired;
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};
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auto ORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal | Desired;
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};
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auto EORDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return SrcVal ^ Desired;
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};
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auto NEGDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return -SrcVal;
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};
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auto SWAPDesired = [](AtomicType SrcVal, AtomicType Desired) -> AtomicType {
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return Desired;
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};
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CASDesiredFn<AtomicType> DesiredFunction{};
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switch (AtomicOp) {
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@ -2089,12 +2073,21 @@ uint64_t HandleAtomicLoadstoreExclusive(void *_ucontext, void *_info) {
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case ExclusiveAtomicPairType::TYPE_AND:
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DesiredFunction = ANDDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_BIC:
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DesiredFunction = BICDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_OR:
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DesiredFunction = ORDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_ORN:
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DesiredFunction = ORNDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_EOR:
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DesiredFunction = EORDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_EON:
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DesiredFunction = EONDesired;
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break;
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case ExclusiveAtomicPairType::TYPE_NEG:
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DesiredFunction = NEGDesired;
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break;
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@ -31,13 +31,19 @@ namespace FEXCore::ArchHelpers::Arm64 {
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constexpr uint32_t CBNZ_MASK = 0x7F'00'00'00;
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constexpr uint32_t CBNZ_INST = 0x35'00'00'00;
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constexpr uint32_t ALU_OP_MASK = 0x7F'00'00'00;
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constexpr uint32_t ADD_INST = 0x0B'00'00'00;
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constexpr uint32_t SUB_INST = 0x4B'00'00'00;
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constexpr uint32_t CMP_INST = 0x6B'00'00'00;
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constexpr uint32_t AND_INST = 0x0A'00'00'00;
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constexpr uint32_t OR_INST = 0x2A'00'00'00;
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constexpr uint32_t EOR_INST = 0x4A'00'00'00;
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constexpr uint32_t ALU_OP_MASK = 0x7F'20'00'00;
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constexpr uint32_t ADD_INST = 0x0B'00'00'00;
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constexpr uint32_t SUB_INST = 0x4B'00'00'00;
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constexpr uint32_t ADD_SHIFT_INST = 0x0B'20'00'00;
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constexpr uint32_t SUB_SHIFT_INST = 0x4B'20'00'00;
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constexpr uint32_t CMP_INST = 0x6B'00'00'00;
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constexpr uint32_t CMP_SHIFT_INST = 0x6B'20'00'00;
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constexpr uint32_t AND_INST = 0x0A'00'00'00;
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constexpr uint32_t BIC_INST = 0x0A'20'00'00;
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constexpr uint32_t OR_INST = 0x2A'00'00'00;
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constexpr uint32_t ORN_INST = 0x2A'20'00'00;
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constexpr uint32_t EOR_INST = 0x4A'00'00'00;
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constexpr uint32_t EON_INST = 0x4A'20'00'00;
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constexpr uint32_t CCMP_MASK = 0x7F'E0'0C'10;
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constexpr uint32_t CCMP_INST = 0x7A'40'00'00;
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@ -50,8 +56,11 @@ namespace FEXCore::ArchHelpers::Arm64 {
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TYPE_ADD,
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TYPE_SUB,
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TYPE_AND,
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TYPE_BIC,
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TYPE_OR,
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TYPE_ORN,
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TYPE_EOR,
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TYPE_EON,
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TYPE_NEG, // This is just a sub with zero. Need to know the differences
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};
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