FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2025-03-06 05:27:18 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge pull request #3466 from Sonicadvance1/fixed_opt

Browse Source 
OpcodeDispatcher: Don't use AddShift with no shift
This commit is contained in:
Ryan Houdek 2024-02-28 04:51:10 -08:00 committed by GitHub
commit d24446ed13
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
3 changed files with 26 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
View File

@ -4757,7 +4757,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
if (!IsVSIB && Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID && Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
auto Base = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize);
auto Index = LoadGPRRegister(Operand.Data.SIB.Index, GPRSize);
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
if (Operand.Data.SIB.Scale == 1) {
Tmp = _Add(IR::SizeToOpSize(GPRSize), Base, Index);
}
else {
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
}
}
else {
// NOTE: VSIB cannot have the index * scale portion calculated ahead of time,
@ -5011,7 +5016,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
if (Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID && Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
auto Base = LoadGPRRegister(Operand.Data.SIB.Base, GPRSize);
auto Index = LoadGPRRegister(Operand.Data.SIB.Index, GPRSize);
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
if (Operand.Data.SIB.Scale == 1) {
Tmp = _Add(IR::SizeToOpSize(GPRSize), Base, Index);
}
else {
Tmp = _AddShift(IR::SizeToOpSize(GPRSize), Base, Index, ShiftType::LSL, FEXCore::ilog2(Operand.Data.SIB.Scale));
}
}
else {
if (Operand.Data.SIB.Index != FEXCore::X86State::REG_INVALID) {

12
unittests/32Bit_ASM/FEX_bugs/SignExtendBug.asm
View File

@ -1,7 +1,8 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "0x41424344"
"RAX": "0x41424344",
"RBX": "0x41424344"
},
"MemoryRegions": {
"0xf0000000": "4096"
@ -17,4 +18,13 @@
lea eax, [0xf000_0000]
mov eax, [ds:eax]
; Ensures that zext occurs correctly with two registers that have the sign bit set.
mov ebx, 0xffff_ffff
mov ecx, 0xf000_0001
; Break the block so it can't optimize through.
jmp .test
.test:
mov ebx, [ebx+ecx]
hlt

8
unittests/InstructionCountCI/FlagM/HotBlocks.json
View File

@ -169,7 +169,7 @@
]
},
"Scalar vector add loop": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 7,
"Comment": [
"Saw this in bytemark"
],
@ -181,11 +181,9 @@
"cmp rsi, rax"
],
"ExpectedArm64ASM": [
"add x20, x16, x4",
"ldr q16, [x20]",
"ldr q16, [x16, x4, sxtx]",
"add v16.2d, v16.2d, v17.2d",
"add x20, x16, x4",
"str q16, [x20]",
"str q16, [x16, x4, sxtx]",
"add x4, x4, #0x10 (16)",
"eor w27, w10, w4",
"subs x26, x10, x4",