From d5beba94233a62e012ce319f2c1f5bd500a8fb8f Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sat, 21 Oct 2023 15:24:43 -0700
Subject: [PATCH] JITArm64: Fixes bug in rpres scalar operations

Noticed this during code investigation, these two operations were
swapped.

Would have caused issues if anything supported RPRES today.
---
 FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
index 7e52eae52..066ca099a 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/VectorOps.cpp
@@ -384,7 +384,7 @@ DEF_OP(VFRSqrtScalarInsert) {
 
   auto ScalarEmitRPRES = [this, SubRegSize](ARMEmitter::VRegister Dst, std::variant<ARMEmitter::VRegister, ARMEmitter::Register> SrcVar) {
     auto Src = *std::get_if<ARMEmitter::VRegister>(&SrcVar);
-    frecpe(SubRegSize.Scalar, Dst.S(), Src.S());
+    frsqrte(SubRegSize.Scalar, Dst.S(), Src.S());
   };
 
   std::array<ScalarUnaryOpCaller, 2> Handlers = {
@@ -421,7 +421,7 @@ DEF_OP(VFRecpScalarInsert) {
 
   auto ScalarEmitRPRES = [this, SubRegSize](ARMEmitter::VRegister Dst, std::variant<ARMEmitter::VRegister, ARMEmitter::Register> SrcVar) {
     auto Src = *std::get_if<ARMEmitter::VRegister>(&SrcVar);
-    frsqrte(SubRegSize.Scalar, Dst, Src);
+    frecpe(SubRegSize.Scalar, Dst, Src);
   };
 
   std::array<ScalarUnaryOpCaller, 2> Handlers = {