From 462b6b8c1c8bae952f21d10bb6e33ac752011ce1 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 01:35:02 +0000 Subject: [PATCH 1/8] OpcodeDispatcher: Handle VMINPS --- .../Interface/Core/OpcodeDispatcher.cpp | 2 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vminps.asm | 43 +++++++++++++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vminps.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index f603ec65a..b4bb18a0e 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5868,6 +5868,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b10, 0x5C), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b11, 0x5C), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, + {OPD(1, 0b00, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x66), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index f7e136822..157c6445e 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -443,6 +443,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 7846a6d2f..6b8da7c84 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -155,7 +155,7 @@ void InitializeVEXTables() { {OPD(1, 0b10, 0x5C), 1, X86InstInfo{"VSUBSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b11, 0x5C), 1, X86InstInfo{"VSUBSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b00, 0x5D), 1, X86InstInfo{"VMINPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b00, 0x5D), 1, X86InstInfo{"VMINPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x5D), 1, X86InstInfo{"VMINPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b10, 0x5D), 1, X86InstInfo{"VMINSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x5D), 1, X86InstInfo{"VMINSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vminps.asm b/unittests/ASM/VEX/vminps.asm new file mode 100644 index 000000000..459dfe99d --- /dev/null +++ b/unittests/ASM/VEX/vminps.asm @@ -0,0 +1,43 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x400000003F800000", "0x4080000040400000", "0x400000003F800000", "0x4080000040400000"], + "XMM1": ["0x40C0000040A00000", "0x4100000040E00000", "0x40C0000040A00000", "0x4100000040E00000"], + "XMM2": ["0x400000003F800000", "0x4080000040400000", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x400000003F800000", "0x4080000040400000", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x400000003F800000", "0x4080000040400000", "0x400000003F800000", "0x4080000040400000"], + "XMM5": ["0x400000003F800000", "0x4080000040400000", "0x400000003F800000", "0x4080000040400000"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] +vmovapd ymm1, [rdx + 32] + +; Memory operand +vminps xmm2, xmm0, [rdx + 32] +vminps ymm4, ymm0, [rdx + 32] + +; Register only +vminps xmm3, xmm0, xmm1 +vminps ymm5, ymm1, ymm0 + +hlt + +align 32 +.data: +dq 0x400000003F800000 ; 2, 1 +dq 0x4080000040400000 ; 4, 3 +dq 0x400000003F800000 ; 2, 1 +dq 0x4080000040400000 ; 4, 3 + +dq 0x40C0000040A00000 ; 6, 5 +dq 0x4100000040E00000 ; 8, 7 +dq 0x40C0000040A00000 ; 6, 5 +dq 0x4100000040E00000 ; 8, 7 From 1689742e96249babbaa020e69dec8f611c2c8600 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 01:51:09 +0000 Subject: [PATCH 2/8] OpcodeDispatcher: Handle VMINPD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vminpd.asm | 43 +++++++++++++++++++ 4 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vminpd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index b4bb18a0e..5753c140a 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5869,6 +5869,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b11, 0x5C), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b00, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b01, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 157c6445e..7f6431ec8 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -445,6 +445,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 6b8da7c84..3379d86f9 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -156,7 +156,7 @@ void InitializeVEXTables() { {OPD(1, 0b11, 0x5C), 1, X86InstInfo{"VSUBSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b00, 0x5D), 1, X86InstInfo{"VMINPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b01, 0x5D), 1, X86InstInfo{"VMINPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b01, 0x5D), 1, X86InstInfo{"VMINPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b10, 0x5D), 1, X86InstInfo{"VMINSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x5D), 1, X86InstInfo{"VMINSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vminpd.asm b/unittests/ASM/VEX/vminpd.asm new file mode 100644 index 000000000..64c7dca1c --- /dev/null +++ b/unittests/ASM/VEX/vminpd.asm @@ -0,0 +1,43 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4008000000000000", "0x4000000000000000", "0x4008000000000000", "0x4000000000000000"], + "XMM1": ["0x3FF0000000000000", "0x4008000000000000", "0x3FF0000000000000", "0x4008000000000000"], + "XMM2": ["0x3FF0000000000000", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x3FF0000000000000", "0x4000000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x3FF0000000000000", "0x4000000000000000", "0x3FF0000000000000", "0x4000000000000000"], + "XMM5": ["0x3FF0000000000000", "0x4000000000000000", "0x3FF0000000000000", "0x4000000000000000"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] +vmovapd ymm1, [rdx + 32] + +; Memory operand +vminpd xmm2, xmm0, [rdx + 32] +vminpd ymm4, ymm0, [rdx + 32] + +; Register only +vminpd xmm3, xmm0, xmm1 +vminpd ymm5, ymm1, ymm0 + +hlt + +align 32 +.data: +dq 0x4008000000000000 +dq 0x4000000000000000 +dq 0x4008000000000000 +dq 0x4000000000000000 + +dq 0x3FF0000000000000 +dq 0x4008000000000000 +dq 0x3FF0000000000000 +dq 0x4008000000000000 From f8d851b9b5b46dec314d428c215ea96962a55fe0 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 02:36:13 +0000 Subject: [PATCH 3/8] OpcodeDispatcher: Handle VMINSS --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vminss.asm | 70 +++++++++++++++++++ 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vminss.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 5753c140a..d77616701 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5870,6 +5870,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b10, 0x5D), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 7f6431ec8..eae9e545d 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -560,6 +560,8 @@ void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 3379d86f9..c3c58fce3 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -157,7 +157,7 @@ void InitializeVEXTables() { {OPD(1, 0b00, 0x5D), 1, X86InstInfo{"VMINPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x5D), 1, X86InstInfo{"VMINPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b10, 0x5D), 1, X86InstInfo{"VMINSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b10, 0x5D), 1, X86InstInfo{"VMINSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b11, 0x5D), 1, X86InstInfo{"VMINSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b00, 0x5E), 1, X86InstInfo{"VDIVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vminss.asm b/unittests/ASM/VEX/vminss.asm new file mode 100644 index 000000000..c16c0e206 --- /dev/null +++ b/unittests/ASM/VEX/vminss.asm @@ -0,0 +1,70 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x414243443F800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM1": ["0x4142434440800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM2": ["0x4142434441100000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM4": ["0x414243443F800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM5": ["0x4142434440800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM7": ["0x4142434441800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM8": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM9": ["0x4142434441C80000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx + 32 * 0] +vmovapd ymm1, [rdx + 32 * 1] +vmovapd ymm2, [rdx + 32 * 2] +vmovapd ymm3, [rdx + 32 * 3] +vmovapd ymm4, [rdx + 32 * 4] + +; Register only +vminss xmm0, xmm0, xmm1 +vminss xmm2, xmm2, xmm3 + +; Memory operand +vminss xmm5, xmm4, [rdx + 32 * 1] +vminss xmm4, xmm4, [rdx + 32 * 0] + +; Merging different src into destination +vpxor xmm7, xmm7, xmm7 +vmovapd ymm8, [rdx + 32 * 3] +vmovapd ymm9, [rdx + 32 * 4] +vminss xmm7, xmm8, xmm9 + +hlt + +align 32 +.data: +dq 0x414243443F800000 ; 1.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434440800000 ; 4.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434441100000 ; 9.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434441800000 ; 16.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434441C80000 ; 25.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 From 92f92ddbbe02666eeb1ba50ae0ba0fa13e13c3a8 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 02:45:17 +0000 Subject: [PATCH 4/8] OpcodeDispatcher: Handle VMINSD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vminsd.asm | 70 +++++++++++++++++++ 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vminsd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index d77616701..6cdba5df7 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5871,6 +5871,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x5D), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b10, 0x5D), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, + {OPD(1, 0b11, 0x5D), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index eae9e545d..e00396835 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -562,6 +562,8 @@ void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index c3c58fce3..731704f04 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -158,7 +158,7 @@ void InitializeVEXTables() { {OPD(1, 0b00, 0x5D), 1, X86InstInfo{"VMINPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x5D), 1, X86InstInfo{"VMINPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b10, 0x5D), 1, X86InstInfo{"VMINSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b11, 0x5D), 1, X86InstInfo{"VMINSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b11, 0x5D), 1, X86InstInfo{"VMINSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b00, 0x5E), 1, X86InstInfo{"VDIVPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b01, 0x5E), 1, X86InstInfo{"VDIVPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vminsd.asm b/unittests/ASM/VEX/vminsd.asm new file mode 100644 index 000000000..68a6ac52e --- /dev/null +++ b/unittests/ASM/VEX/vminsd.asm @@ -0,0 +1,70 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x3FF0000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM1": ["0x4010000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM2": ["0x4022000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x4030000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM4": ["0x3FF0000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM5": ["0x4010000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM7": ["0x4030000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM8": ["0x4030000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM9": ["0x4039000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx + 32 * 0] +vmovapd ymm1, [rdx + 32 * 1] +vmovapd ymm2, [rdx + 32 * 2] +vmovapd ymm3, [rdx + 32 * 3] +vmovapd ymm4, [rdx + 32 * 4] + +; Register only +vminsd xmm0, xmm0, xmm1 +vminsd xmm2, xmm2, xmm3 + +; Memory operand +vminsd xmm5, xmm4, [rdx + 32 * 1] +vminsd xmm4, xmm4, [rdx + 32 * 0] + +; Merging different src into destination +vpxor xmm7, xmm7, xmm7 +vmovapd ymm8, [rdx + 32 * 3] +vmovapd ymm9, [rdx + 32 * 4] +vminsd xmm7, xmm8, xmm9 + +hlt + +align 32 +.data: +dq 0x3FF0000000000000 ; 1.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4010000000000000 ; 4.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4022000000000000 ; 9.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4030000000000000 ; 16.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4039000000000000 ; 25.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 From b7e177c11cb54f8730c34991277e36f556b0afe4 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 02:51:19 +0000 Subject: [PATCH 5/8] OpcodeDispatcher: Handle VMAXPS --- .../Interface/Core/OpcodeDispatcher.cpp | 2 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vmaxps.asm | 43 +++++++++++++++++++ 4 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vmaxps.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 6cdba5df7..7b6bb4824 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5873,6 +5873,8 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b10, 0x5D), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b11, 0x5D), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, + {OPD(1, 0b00, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x66), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index e00396835..05a816de9 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -443,6 +443,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 731704f04..b3f01e730 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -165,7 +165,7 @@ void InitializeVEXTables() { {OPD(1, 0b10, 0x5E), 1, X86InstInfo{"VDIVSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x5E), 1, X86InstInfo{"VDIVSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, - {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x5F), 1, X86InstInfo{"VMAXPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b10, 0x5F), 1, X86InstInfo{"VMAXSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x5F), 1, X86InstInfo{"VMAXSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vmaxps.asm b/unittests/ASM/VEX/vmaxps.asm new file mode 100644 index 000000000..2aed4f9d3 --- /dev/null +++ b/unittests/ASM/VEX/vmaxps.asm @@ -0,0 +1,43 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x400000003F800000", "0x4080000040400000", "0x400000003F800000", "0x4080000040400000"], + "XMM1": ["0x40C0000040A00000", "0x4100000040E00000", "0x40C0000040A00000", "0x4100000040E00000"], + "XMM2": ["0x40C0000040A00000", "0x4100000040E00000", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x40C0000040A00000", "0x4100000040E00000", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x40C0000040A00000", "0x4100000040E00000", "0x40C0000040A00000", "0x4100000040E00000"], + "XMM5": ["0x40C0000040A00000", "0x4100000040E00000", "0x40C0000040A00000", "0x4100000040E00000"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] +vmovapd ymm1, [rdx + 32] + +; Memory operand +vmaxps xmm2, xmm0, [rdx + 32] +vmaxps ymm4, ymm0, [rdx + 32] + +; Register only +vmaxps xmm3, xmm0, xmm1 +vmaxps ymm5, ymm1, ymm0 + +hlt + +align 32 +.data: +dq 0x400000003F800000 ; 2, 1 +dq 0x4080000040400000 ; 4, 3 +dq 0x400000003F800000 ; 2, 1 +dq 0x4080000040400000 ; 4, 3 + +dq 0x40C0000040A00000 ; 6, 5 +dq 0x4100000040E00000 ; 8, 7 +dq 0x40C0000040A00000 ; 6, 5 +dq 0x4100000040E00000 ; 8, 7 From 3590f090c726643b0e720e9552a587147c4315ef Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 02:57:13 +0000 Subject: [PATCH 6/8] OpcodeDispatcher: Handle VMAXPD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vmaxpd.asm | 43 +++++++++++++++++++ 4 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vmaxpd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 7b6bb4824..3dc2531a0 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5874,6 +5874,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b11, 0x5D), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b00, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b01, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 05a816de9..7244fe0a7 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -445,6 +445,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index b3f01e730..793ec68d7 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -166,7 +166,7 @@ void InitializeVEXTables() { {OPD(1, 0b11, 0x5E), 1, X86InstInfo{"VDIVSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b01, 0x5F), 1, X86InstInfo{"VMAXPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b01, 0x5F), 1, X86InstInfo{"VMAXPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b10, 0x5F), 1, X86InstInfo{"VMAXSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, {OPD(1, 0b11, 0x5F), 1, X86InstInfo{"VMAXSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vmaxpd.asm b/unittests/ASM/VEX/vmaxpd.asm new file mode 100644 index 000000000..408b5f020 --- /dev/null +++ b/unittests/ASM/VEX/vmaxpd.asm @@ -0,0 +1,43 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4008000000000000", "0x4000000000000000", "0x4008000000000000", "0x4000000000000000"], + "XMM1": ["0x3FF0000000000000", "0x4008000000000000", "0x3FF0000000000000", "0x4008000000000000"], + "XMM2": ["0x4008000000000000", "0x4008000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x4008000000000000", "0x4008000000000000", "0x0000000000000000", "0x0000000000000000"], + "XMM4": ["0x4008000000000000", "0x4008000000000000", "0x4008000000000000", "0x4008000000000000"], + "XMM5": ["0x4008000000000000", "0x4008000000000000", "0x4008000000000000", "0x4008000000000000"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx] +vmovapd ymm1, [rdx + 32] + +; Memory operand +vmaxpd xmm2, xmm0, [rdx + 32] +vmaxpd ymm4, ymm0, [rdx + 32] + +; Register only +vmaxpd xmm3, xmm0, xmm1 +vmaxpd ymm5, ymm1, ymm0 + +hlt + +align 32 +.data: +dq 0x4008000000000000 +dq 0x4000000000000000 +dq 0x4008000000000000 +dq 0x4000000000000000 + +dq 0x3FF0000000000000 +dq 0x4008000000000000 +dq 0x3FF0000000000000 +dq 0x4008000000000000 From 42d24c21e15ecf8da867a64c7cc30b3907e3ac72 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 03:01:08 +0000 Subject: [PATCH 7/8] OpcodeDispatcher: Handle VMAXSS --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vmaxss.asm | 70 +++++++++++++++++++ 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vmaxss.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 3dc2531a0..481fc48ac 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5875,6 +5875,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, + {OPD(1, 0b10, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 7244fe0a7..dd8800cdb 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -564,6 +564,8 @@ void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index 793ec68d7..a03bd2c10 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -167,7 +167,7 @@ void InitializeVEXTables() { {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x5F), 1, X86InstInfo{"VMAXPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b10, 0x5F), 1, X86InstInfo{"VMAXSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b10, 0x5F), 1, X86InstInfo{"VMAXSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b11, 0x5F), 1, X86InstInfo{"VMAXSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vmaxss.asm b/unittests/ASM/VEX/vmaxss.asm new file mode 100644 index 000000000..96eeb9b03 --- /dev/null +++ b/unittests/ASM/VEX/vmaxss.asm @@ -0,0 +1,70 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4142434440800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM1": ["0x4142434440800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM2": ["0x4142434441800000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM4": ["0x4142434441C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM5": ["0x4142434441C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM7": ["0x4142434441C80000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM8": ["0x4142434441800000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM9": ["0x4142434441C80000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx + 32 * 0] +vmovapd ymm1, [rdx + 32 * 1] +vmovapd ymm2, [rdx + 32 * 2] +vmovapd ymm3, [rdx + 32 * 3] +vmovapd ymm4, [rdx + 32 * 4] + +; Register only +vmaxss xmm0, xmm0, xmm1 +vmaxss xmm2, xmm2, xmm3 + +; Memory operand +vmaxss xmm5, xmm4, [rdx + 32 * 1] +vmaxss xmm4, xmm4, [rdx + 32 * 0] + +; Merging different src into destination +vpxor xmm7, xmm7, xmm7 +vmovapd ymm8, [rdx + 32 * 3] +vmovapd ymm9, [rdx + 32 * 4] +vmaxss xmm7, xmm8, xmm9 + +hlt + +align 32 +.data: +dq 0x414243443F800000 ; 1.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434440800000 ; 4.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434441100000 ; 9.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434441800000 ; 16.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4142434441C80000 ; 25.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 From e1de89af7970a1833f237ac4ec04d911baffacd0 Mon Sep 17 00:00:00 2001 From: lioncash Date: Tue, 13 Dec 2022 03:05:25 +0000 Subject: [PATCH 8/8] OpcodeDispatcher: Handle VMAXSD --- .../Interface/Core/OpcodeDispatcher.cpp | 1 + .../Core/OpcodeDispatcher/Vector.cpp | 2 + .../Interface/Core/X86Tables/VEXTables.cpp | 2 +- unittests/ASM/VEX/vmaxsd.asm | 70 +++++++++++++++++++ 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 unittests/ASM/VEX/vmaxsd.asm diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 481fc48ac..50fe29f09 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -5876,6 +5876,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() { {OPD(1, 0b00, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x5F), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b10, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, + {OPD(1, 0b11, 0x5F), 1, &OpDispatchBuilder::AVXVectorScalarALUOp}, {OPD(1, 0b01, 0x64), 1, &OpDispatchBuilder::AVXVectorALUOp}, {OPD(1, 0b01, 0x65), 1, &OpDispatchBuilder::AVXVectorALUOp}, diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index dd8800cdb..22c10dd47 100644 --- a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -566,6 +566,8 @@ void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template +void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); +template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); template void OpDispatchBuilder::AVXVectorScalarALUOp(OpcodeArgs); diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp index a03bd2c10..cfa869ae1 100644 --- a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp +++ b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp @@ -168,7 +168,7 @@ void InitializeVEXTables() { {OPD(1, 0b00, 0x5F), 1, X86InstInfo{"VMAXPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x5F), 1, X86InstInfo{"VMAXPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b10, 0x5F), 1, X86InstInfo{"VMAXSS", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_32BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, - {OPD(1, 0b11, 0x5F), 1, X86InstInfo{"VMAXSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, + {OPD(1, 0b11, 0x5F), 1, X86InstInfo{"VMAXSD", TYPE_INST, GenFlagsSizes(SIZE_128BIT, SIZE_64BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}}, {OPD(1, 0b01, 0x68), 1, X86InstInfo{"VPUNPCKHBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}}, diff --git a/unittests/ASM/VEX/vmaxsd.asm b/unittests/ASM/VEX/vmaxsd.asm new file mode 100644 index 000000000..e42ad2c46 --- /dev/null +++ b/unittests/ASM/VEX/vmaxsd.asm @@ -0,0 +1,70 @@ +%ifdef CONFIG +{ + "HostFeatures": ["AVX"], + "RegData": { + "XMM0": ["0x4010000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM1": ["0x4010000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM2": ["0x4030000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM3": ["0x4030000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM4": ["0x4039000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM5": ["0x4039000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM7": ["0x4039000000000000", "0x5152535455565758", "0x0000000000000000", "0x0000000000000000"], + "XMM8": ["0x4030000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"], + "XMM9": ["0x4039000000000000", "0x5152535455565758", "0x5152535455565758", "0x5152535455565758"] + }, + "MemoryRegions": { + "0x100000000": "4096" + } +} +%endif + +lea rdx, [rel .data] + +vmovapd ymm0, [rdx + 32 * 0] +vmovapd ymm1, [rdx + 32 * 1] +vmovapd ymm2, [rdx + 32 * 2] +vmovapd ymm3, [rdx + 32 * 3] +vmovapd ymm4, [rdx + 32 * 4] + +; Register only +vmaxsd xmm0, xmm0, xmm1 +vmaxsd xmm2, xmm2, xmm3 + +; Memory operand +vmaxsd xmm5, xmm4, [rdx + 32 * 1] +vmaxsd xmm4, xmm4, [rdx + 32 * 0] + +; Merging different src into destination +vpxor xmm7, xmm7, xmm7 +vmovapd ymm8, [rdx + 32 * 3] +vmovapd ymm9, [rdx + 32 * 4] +vmaxsd xmm7, xmm8, xmm9 + +hlt + +align 32 +.data: +dq 0x3FF0000000000000 ; 1.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4010000000000000 ; 4.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4022000000000000 ; 9.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4030000000000000 ; 16.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758 + +dq 0x4039000000000000 ; 25.0 +dq 0x5152535455565758 +dq 0x5152535455565758 +dq 0x5152535455565758