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OpcodeDispatcher: Handle VADDPD

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This commit is contained in:
lioncash 2022-12-05 16:45:43 +00:00
parent a8571282b2
commit e7f54d1592
4 changed files with 46 additions and 1 deletions
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1
External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp vendored
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@ -5840,6 +5840,7 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
{OPD(1, 0b01, 0x57), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VXOR, 16>},
{OPD(1, 0b00, 0x58), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFADD, 4>},
{OPD(1, 0b01, 0x58), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFADD, 8>},
{OPD(1, 0b01, 0x6E), 1, &OpDispatchBuilder::MOVBetweenGPR_FPR},

2
External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp vendored
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@ -411,6 +411,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs) {
template
void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFADD, 4>(OpcodeArgs);
template
void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VFADD, 8>(OpcodeArgs);
template
void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VAND, 16>(OpcodeArgs);

2
External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp vendored
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@ -137,7 +137,7 @@ void InitializeVEXTables() {
{OPD(1, 0b01, 0x2F), 1, X86InstInfo{"VUCOMISD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b00, 0x58), 1, X86InstInfo{"VADDPS", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b01, 0x58), 1, X86InstInfo{"VADDPD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b01, 0x58), 1, X86InstInfo{"VADDPD", TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
{OPD(1, 0b10, 0x58), 1, X86InstInfo{"VADDSS", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
{OPD(1, 0b11, 0x58), 1, X86InstInfo{"VADDSD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

42
unittests/ASM/VEX/vaddpd.asm Normal file
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@ -0,0 +1,42 @@
%ifdef CONFIG
{
"HostFeatures": ["AVX"],
"RegData": {
"XMM0": ["0x3FF0000000000000", "0x4000000000000000", "0x4008000000000000", "0x4010000000000000"],
"XMM1": ["0x4014000000000000", "0x4018000000000000", "0x401C000000000000", "0x4020000000000000"],
"XMM2": ["0x4018000000000000", "0x4020000000000000", "0x4024000000000000", "0x4028000000000000"],
"XMM3": ["0x4018000000000000", "0x4020000000000000", "0x0000000000000000", "0x0000000000000000"],
"XMM4": ["0x4018000000000000", "0x4020000000000000", "0x4024000000000000", "0x4028000000000000"],
"XMM5": ["0x4018000000000000", "0x4020000000000000", "0x0000000000000000", "0x0000000000000000"]
},
"MemoryRegions": {
"0x100000000": "4096"
}
}
%endif
lea rdx, [rel .data]
; Registers
vmovapd ymm0, [rdx]
vmovapd ymm1, [rdx + 32]
vaddpd ymm2, ymm0, ymm1
vaddpd xmm3, xmm0, xmm1
; Memory operand
vaddpd ymm4, ymm0, [rdx + 32]
vaddpd xmm5, xmm0, [rdx + 32]
hlt
align 32
.data:
dq 0x3FF0000000000000 ; 1.0
dq 0x4000000000000000 ; 2.0
dq 0x4008000000000000 ; 3.0
dq 0x4010000000000000 ; 4.0
dq 0x4014000000000000 ; 5.0
dq 0x4018000000000000 ; 6.0
dq 0x401C000000000000 ; 7.0
dq 0x4020000000000000 ; 8.0