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https://github.com/FEX-Emu/FEX.git
synced 2025-01-20 21:37:20 +00:00
Fixes x86 instruction decoding.
In the case of modrm + immediate then the immediate would end up overwriting Src1 due to the the order of the decoding. Changes Src1 and Src2 to an array and use a variable to index the array. Causes a bit of code churn but fixes instruction decoding and allows easier expansion in the future for instructions that have more sources like AVX
This commit is contained in:
Ryan Houdek
Stefanos Kornilios Mitsis Poiitidis
parent
9135661861
commit
ed12a8a242
@ -298,7 +298,7 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
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CurrentDest->TypeGPR.Type = DecodedOperand::TYPE_GPR;
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CurrentDest->TypeGPR.HighBits = false;
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CurrentDest->TypeGPR.GPR = HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_DST_RAX) ? FEXCore::X86State::REG_RAX : FEXCore::X86State::REG_RDX;
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CurrentDest = &DecodeInst->Src1;
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CurrentDest = &DecodeInst->Src[0];
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}
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if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_REX_IN_BYTE)) {
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@ -408,36 +408,35 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
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}
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};
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if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM &&
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Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SF_MOD_DST) {
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ModRMOperand(DecodeInst->Src1, DecodeInst->Dest, HasXMMSrc, HasXMMDst, Is8BitSrc, Is8BitDest);
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size_t CurrentSrc = 0;
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if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM) {
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if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SF_MOD_DST) {
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ModRMOperand(DecodeInst->Src[CurrentSrc], DecodeInst->Dest, HasXMMSrc, HasXMMDst, Is8BitSrc, Is8BitDest);
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}
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else {
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ModRMOperand(DecodeInst->Dest, DecodeInst->Src[CurrentSrc], HasXMMDst, HasXMMSrc, Is8BitDest, Is8BitSrc);
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}
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++CurrentSrc;
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}
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// This is almost the same as when the ModRM is the destination type
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// The main different being that Dst and Src flip which bits that use (reg<->rm)
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auto *CurrentSrc = &DecodeInst->Src1;
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if (Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM &&
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!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_SF_MOD_DST)) {
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ModRMOperand(DecodeInst->Dest, DecodeInst->Src1, HasXMMDst, HasXMMSrc, Is8BitDest, Is8BitSrc);
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CurrentSrc = &DecodeInst->Src2;
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}
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else if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RAX)) {
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CurrentSrc->TypeGPR.Type = DecodedOperand::TYPE_GPR;
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CurrentSrc->TypeGPR.HighBits = false;
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CurrentSrc->TypeGPR.GPR = FEXCore::X86State::REG_RAX;
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CurrentSrc = &DecodeInst->Src2;
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if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RAX)) {
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DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
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DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
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DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RAX;
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++CurrentSrc;
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}
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else if (HAS_NON_XMM_SUBFLAG(Info->Flags, FEXCore::X86Tables::InstFlags::FLAGS_SF_SRC_RCX)) {
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CurrentSrc->TypeGPR.Type = DecodedOperand::TYPE_GPR;
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CurrentSrc->TypeGPR.HighBits = false;
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CurrentSrc->TypeGPR.GPR = FEXCore::X86State::REG_RCX;
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CurrentSrc = &DecodeInst->Src2;
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DecodeInst->Src[CurrentSrc].TypeGPR.Type = DecodedOperand::TYPE_GPR;
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DecodeInst->Src[CurrentSrc].TypeGPR.HighBits = false;
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DecodeInst->Src[CurrentSrc].TypeGPR.GPR = FEXCore::X86State::REG_RCX;
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++CurrentSrc;
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}
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if (Bytes != 0) {
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LogMan::Throw::A(Bytes <= 8, "Number of bytes should be <= 8 for literal src");
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CurrentSrc->TypeLiteral.Size = Bytes;
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DecodeInst->Src[CurrentSrc].TypeLiteral.Size = Bytes;
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uint64_t Literal {0};
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Literal = ReadData(Bytes);
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@ -455,8 +454,8 @@ bool Decoder::NormalOp(FEXCore::X86Tables::X86InstInfo const *Info, uint16_t Op)
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}
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Bytes = 0;
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CurrentSrc->TypeLiteral.Type = DecodedOperand::TYPE_LITERAL;
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CurrentSrc->TypeLiteral.Literal = Literal;
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DecodeInst->Src[CurrentSrc].TypeLiteral.Type = DecodedOperand::TYPE_LITERAL;
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DecodeInst->Src[CurrentSrc].TypeLiteral.Literal = Literal;
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}
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LogMan::Throw::A(Bytes == 0, "Inst at 0x%lx: 0x%04x '%s' Had an instruction of size %d with %d remaining", DecodeInst->PC, DecodeInst->OP, DecodeInst->TableInfo->Name, InstructionSize, Bytes);
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@ -835,17 +834,17 @@ void Decoder::BranchTargetInMultiblockRange() {
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case 0x70 ... 0x7F: // Conditional JUMP
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case 0x80 ... 0x8F: { // More conditional
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// Source is a literal
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// auto RIPOffset = LoadSource(Op, Op->Src1, Op->Flags);
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// auto RIPOffset = LoadSource(Op, Op->Src[0], Op->Flags);
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// auto RIPTargetConst = _Constant(Op->PC + Op->InstSize);
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// Target offset is PC + InstSize + Literal
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LogMan::Throw::A(DecodeInst->Src1.TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
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TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src1.TypeLiteral.Literal;
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LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
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TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
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break;
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}
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case 0xE9:
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case 0xEB: // Both are unconditional JMP instructions
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LogMan::Throw::A(DecodeInst->Src1.TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
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TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src1.TypeLiteral.Literal;
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LogMan::Throw::A(DecodeInst->Src[0].TypeNone.Type == DecodedOperand::TYPE_LITERAL, "Had wrong operand type");
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TargetRIP = DecodeInst->PC + DecodeInst->InstSize + DecodeInst->Src[0].TypeLiteral.Literal;
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Conditional = false;
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break;
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case 0xC2: // RET imm
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File diff suppressed because it is too large
Load Diff
@ -95,16 +95,21 @@ public:
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// Dispatch builder functions
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#define OpcodeArgs [[maybe_unused]] FEXCore::X86Tables::DecodedOp Op
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void UnhandledOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void MOVGPROp(OpcodeArgs);
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void MOVVectorOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void ALUOp(OpcodeArgs);
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void INTOp(OpcodeArgs);
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void SyscallOp(OpcodeArgs);
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void LEAOp(OpcodeArgs);
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void NOPOp(OpcodeArgs);
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void RETOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void SecondaryALUOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void ADCOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void SBBOp(OpcodeArgs);
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void PUSHOp(OpcodeArgs);
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void POPOp(OpcodeArgs);
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@ -114,10 +119,12 @@ public:
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void CondJUMPOp(OpcodeArgs);
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void JUMPOp(OpcodeArgs);
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void JUMPAbsoluteOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void TESTOp(OpcodeArgs);
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void MOVSXDOp(OpcodeArgs);
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void MOVSXOp(OpcodeArgs);
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void MOVZXOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void CMPOp(OpcodeArgs);
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void SETccOp(OpcodeArgs);
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void CQOOp(OpcodeArgs);
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@ -137,11 +144,17 @@ public:
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void SHLDOp(OpcodeArgs);
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void SHRDOp(OpcodeArgs);
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void ASHROp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void ROROp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void ROLOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void BTOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void BTROp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void BTSOp(OpcodeArgs);
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template<uint32_t SrcIndex>
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void BTCOp(OpcodeArgs);
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void IMUL1SrcOp(OpcodeArgs);
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void IMUL2SrcOp(OpcodeArgs);
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@ -186,7 +199,9 @@ public:
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void PMAXUOp(OpcodeArgs);
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void PMINSWOp(OpcodeArgs);
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void PMOVMSKBOp(OpcodeArgs);
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template<size_t ElementSize>
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void PUNPCKLOp(OpcodeArgs);
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template<size_t ElementSize>
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void PUNPCKHOp(OpcodeArgs);
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template<size_t ElementSize, bool Low>
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void PSHUFDOp(OpcodeArgs);
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@ -194,9 +209,9 @@ public:
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template<size_t ElementSize>
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void PCMPGTOp(OpcodeArgs);
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void MOVDOp(OpcodeArgs);
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template<size_t ElementSize>
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template<size_t ElementSize, uint32_t SrcIndex>
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void PSRLD(OpcodeArgs);
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template<size_t ElementSize, bool Scalar>
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template<size_t ElementSize, bool Scalar, uint32_t SrcIndex>
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void PSLL(OpcodeArgs);
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void PSRLDQ(OpcodeArgs);
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void PSLLDQ(OpcodeArgs);
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@ -110,8 +110,7 @@ struct DecodedInst {
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bool DecodedSIB;
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DecodedOperand Dest;
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DecodedOperand Src1;
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DecodedOperand Src2;
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DecodedOperand Src[2];
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// Constains the dispatcher handler pointer
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X86InstInfo const* TableInfo;
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