FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2024-12-04 04:22:25 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

IR: Change VUShrI to use IR::OpSize

Browse Source
This commit is contained in:
Ryan Houdek 2024-10-27 22:57:57 -07:00
parent 9b981a4f61
commit ed313edd07
No known key found for this signature in database
4 changed files with 25 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
FEXCore/Source/Interface/Core/OpcodeDispatcher.h
View File

@ -450,7 +450,7 @@ public:
void PSHUFW8ByteOp(OpcodeArgs);
void PSHUFDOp(OpcodeArgs);
void PSRLDOp(OpcodeArgs, size_t ElementSize);
void PSRLI(OpcodeArgs, size_t ElementSize);
void PSRLI(OpcodeArgs, IR::OpSize ElementSize);
void PSLLI(OpcodeArgs, IR::OpSize ElementSize);
void PSLL(OpcodeArgs, size_t ElementSize);
void PSRAOp(OpcodeArgs, size_t ElementSize);
@ -681,7 +681,7 @@ public:
void VPUNPCKLOp(OpcodeArgs, size_t ElementSize);
void VPSRLIOp(OpcodeArgs, size_t ElementSize);
void VPSRLIOp(OpcodeArgs, IR::OpSize ElementSize);
void VSHUFOp(OpcodeArgs, IR::OpSize ElementSize);
@ -941,7 +941,7 @@ public:
void AVX128_VectorBinaryImpl(OpcodeArgs, size_t SrcSize, IR::OpSize ElementSize,
std::function<Ref(IR::OpSize ElementSize, Ref Src1, Ref Src2)> Helper);
void AVX128_VectorShiftWideImpl(OpcodeArgs, size_t ElementSize, IROps IROp);
void AVX128_VectorShiftImmImpl(OpcodeArgs, size_t ElementSize, IROps IROp);
void AVX128_VectorShiftImmImpl(OpcodeArgs, IR::OpSize ElementSize, IROps IROp);
void AVX128_VectorTrinaryImpl(OpcodeArgs, size_t SrcSize, size_t ElementSize, Ref Src3,
std::function<Ref(size_t ElementSize, Ref Src1, Ref Src2, Ref Src3)> Helper);

26
FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
View File

@ -428,25 +428,33 @@ void OpDispatchBuilder::InstallAVX128Handlers() {
#define OPD(group, pp, opcode) (((group - X86Tables::TYPE_VEX_GROUP_12) << 4) | (pp << 3) | (opcode))
static constexpr std::tuple<uint8_t, uint8_t, X86Tables::OpDispatchPtr> VEX128TableGroupOps[] {
// VPSRLI
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b010), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 2, IROps::OP_VUSHRI>},
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b010), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i16Bit, IROps::OP_VUSHRI>},
// VPSLLI
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b110), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 2, IROps::OP_VSHLI>},
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b110), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i16Bit, IROps::OP_VSHLI>},
// VPSRAI
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b100), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 2, IROps::OP_VSSHRI>},
{OPD(X86Tables::TYPE_VEX_GROUP_12, 1, 0b100), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i16Bit, IROps::OP_VSSHRI>},
// VPSRLI
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b010), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 4, IROps::OP_VUSHRI>},
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b010), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i32Bit, IROps::OP_VUSHRI>},
// VPSLLI
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b110), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 4, IROps::OP_VSHLI>},
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b110), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i32Bit, IROps::OP_VSHLI>},
// VPSRAI
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b100), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 4, IROps::OP_VSSHRI>},
{OPD(X86Tables::TYPE_VEX_GROUP_13, 1, 0b100), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i32Bit, IROps::OP_VSSHRI>},
// VPSRLI
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b010), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 8, IROps::OP_VUSHRI>},
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b010), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i64Bit, IROps::OP_VUSHRI>},
// VPSRLDQ
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b011), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ShiftDoubleImm, ShiftDirection::RIGHT>},
// VPSLLI
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b110), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, 8, IROps::OP_VSHLI>},
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b110), 1,
&OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_VectorShiftImmImpl, OpSize::i64Bit, IROps::OP_VSHLI>},
// VPSLLDQ
{OPD(X86Tables::TYPE_VEX_GROUP_14, 1, 0b111), 1, &OpDispatchBuilder::Bind<&OpDispatchBuilder::AVX128_ShiftDoubleImm, ShiftDirection::LEFT>},
@ -730,7 +738,7 @@ void OpDispatchBuilder::AVX128_VectorShiftWideImpl(OpcodeArgs, size_t ElementSiz
AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
}
void OpDispatchBuilder::AVX128_VectorShiftImmImpl(OpcodeArgs, size_t ElementSize, IROps IROp) {
void OpDispatchBuilder::AVX128_VectorShiftImmImpl(OpcodeArgs, IR::OpSize ElementSize, IROps IROp) {
const auto DstSize = GetDstSize(Op);
const auto Is128Bit = DstSize == Core::CPUState::XMM_SSE_REG_SIZE;
const uint64_t ShiftConstant = Op->Src[1].Literal();

8
FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
View File

@ -1709,22 +1709,22 @@ void OpDispatchBuilder::VPSRLDOp(OpcodeArgs, size_t ElementSize) {
StoreResult(FPRClass, Op, Result, OpSize::iInvalid);
}
void OpDispatchBuilder::PSRLI(OpcodeArgs, size_t ElementSize) {
void OpDispatchBuilder::PSRLI(OpcodeArgs, IR::OpSize ElementSize) {
const uint64_t ShiftConstant = Op->Src[1].Literal();
if (ShiftConstant == 0) [[unlikely]] {
// Nothing to do, value is already in Dest.
return;
}
const auto Size = GetSrcSize(Op);
const auto Size = OpSizeFromSrc(Op);
Ref Dest = LoadSource(FPRClass, Op, Op->Dest, Op->Flags);
Ref Shift = _VUShrI(Size, ElementSize, Dest, ShiftConstant);
StoreResult(FPRClass, Op, Shift, OpSize::iInvalid);
}
void OpDispatchBuilder::VPSRLIOp(OpcodeArgs, size_t ElementSize) {
const auto Size = GetSrcSize(Op);
void OpDispatchBuilder::VPSRLIOp(OpcodeArgs, IR::OpSize ElementSize) {
const auto Size = OpSizeFromSrc(Op);
const auto Is128Bit = Size == Core::CPUState::XMM_SSE_REG_SIZE;
const uint64_t ShiftConstant = Op->Src[1].Literal();

2
FEXCore/Source/Interface/IR/IR.json
View File

@ -1997,7 +1997,7 @@
"DestSize": "RegisterSize",
"NumElements": "RegisterSize / ElementSize"
},
"FPR = VUShrI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
"FPR = VUShrI OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Vector, u8:$BitShift": {
"TiedSource": 0,
"DestSize": "RegisterSize",
"NumElements": "RegisterSize / ElementSize"