From f078b25c7de8bbce898716b29dc2b6bfc69bc1f9 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Wed, 14 Aug 2024 21:04:47 -0400
Subject: [PATCH] InstructionCountCI: add bytemark huffman blocks

this test case has our biggest delta to native by far. the trash code we emit
makes clear why!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 .../InstructionCountCI/FlagM/HotBlocks.json   | 159 ++++++++++++++++++
 1 file changed, 159 insertions(+)

diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json
index 10c786d1a..09ca075ea 100644
--- a/unittests/InstructionCountCI/FlagM/HotBlocks.json
+++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json
@@ -283,6 +283,165 @@
         "subs w26, w4, #0x18 (24)"
       ]
     },
+    "bytemark huffman 1": {
+      "ExpectedInstructionCount": 25,
+      "x86Insts": [
+        "mov    r9,rdx",
+        "mov    r8,rcx",
+        "nop    dword [rax+0x0]",
+        "mov    r10d,esi",
+        "shr    r10d,0x3",
+        "movzx  r10d,byte [rbp+r10*1+0x0]",
+        "mov    r11d,esi",
+        "and    r11d,0x7",
+        "bt     r10d,r11d",
+        "lea    r8,[r8+r8*4]",
+        "lea    r8,[rbx+r8*4+0x10]",
+        "cmovae r8,r9",
+        "movsxd r8,dword [r8]",
+        "add    rsi,0x1",
+        "lea    r10,[r8+r8*4]",
+        "lea    r9,[rbx+r10*4]",
+        "add    r9,0xc",
+        "cmp    dword [rbx+r10*4+0xc],0xffffffff"
+      ],
+      "ExpectedArm64ASM": [
+        "mov x13, x6",
+        "mov x12, x5",
+        "mov w14, w10",
+        "lsr w14, w14, #3",
+        "ldrb w14, [x9, x14, sxtx]",
+        "mov w15, w10",
+        "and w15, w15, #0x7",
+        "lsr w20, w14, w15",
+        "eor x20, x20, #0x1",
+        "rmif x20, #63, #nzCv",
+        "add x12, x12, x12, lsl #2",
+        "add x20, x7, #0x10 (16)",
+        "add x12, x20, x12, lsl #2",
+        "csel x12, x13, x12, hs",
+        "ldr w20, [x12]",
+        "sxtw x12, w20",
+        "add x10, x10, #0x1 (1)",
+        "add x14, x12, x12, lsl #2",
+        "add x13, x7, x14, lsl #2",
+        "add x13, x13, #0xc (12)",
+        "mov w20, #0xffffffff",
+        "add x21, x7, x14, lsl #2",
+        "ldr w21, [x21, #12]",
+        "mvn w27, w21",
+        "subs w26, w21, w20"
+      ]
+    },
+    "bytemark huffman 2": {
+      "ExpectedInstructionCount": 19,
+      "x86Insts": [
+        "movsxd r9,r8d",
+        "lea    r9,[r9+r9*4]",
+        "cmp    dword [rbx+r9*4+0xc],ecx",
+        "sete   cl",
+        "xor    cl,0x31",
+        "mov    byte [rsp+rdi*1+0x50],cl",
+        "add    rdi,0x1",
+        "mov    ecx,r8d",
+        "mov    r8d,dword [rbx+r9*4+0x8]",
+        "cmp    r8d,0xfffffffe"
+      ],
+      "ExpectedArm64ASM": [
+        "sxtw x13, w12",
+        "add x13, x13, x13, lsl #2",
+        "add x20, x7, x13, lsl #2",
+        "ldr w20, [x20, #12]",
+        "subs w20, w20, w5",
+        "cset x21, eq",
+        "bfxil x5, x21, #0, #8",
+        "mov w21, #0x31",
+        "eor w21, w5, w21",
+        "bfxil x5, x21, #0, #8",
+        "add x21, x8, x11",
+        "strb w5, [x21, #80]",
+        "add x11, x11, #0x1 (1)",
+        "mov w5, w12",
+        "add x21, x7, x13, lsl #2",
+        "ldr w12, [x21, #8]",
+        "mov w21, #0xfffffffe",
+        "mvn w27, w12",
+        "subs w26, w12, w21"
+      ]
+    },
+    "bytemark huffman 3": {
+      "ExpectedInstructionCount": 47,
+      "x86Insts": [
+        "mov    ecx,eax",
+        "and    cl,0x7",
+        "mov    r8b,0x1",
+        "shl    r8b,cl",
+        "mov    r9d,eax",
+        "shr    r9d,0x3",
+        "movzx  r10d,byte [rbp+r9*1+0x0]",
+        "mov    r11b,0xfe",
+        "mov    ecx,eax",
+        "rol    r11b,cl",
+        "and    r11b,r10b",
+        "or     r8b,r10b",
+        "cmp    byte [rsp+rdi*1+0x4f],0x31",
+        "movzx  ecx,r8b",
+        "movzx  r8d,r11b",
+        "cmove  r8d,ecx",
+        "add    rax,0x1",
+        "mov    byte [rbp+r9*1+0x0],r8b",
+        "add    rdi,0xffffffffffffffff"
+      ],
+      "ExpectedArm64ASM": [
+        "mov w5, w4",
+        "and w20, w5, #0x7",
+        "bfxil x5, x20, #0, #8",
+        "mov w20, #0x1",
+        "bfxil x12, x20, #0, #8",
+        "lsl w20, w12, w5",
+        "bfxil x12, x20, #0, #8",
+        "mov w13, w4",
+        "lsr w26, w13, #3",
+        "cmp w26, #0x0 (0)",
+        "eor x20, x13, #0x4",
+        "rmif x20, #1, #nzCv",
+        "mov x13, x26",
+        "ldrb w14, [x9, x13, sxtx]",
+        "mov w20, #0xfe",
+        "bfxil x15, x20, #0, #8",
+        "mov w5, w4",
+        "and x20, x5, #0x1f",
+        "cbz x20, #+0x2c",
+        "mov w20, w15",
+        "bfi w20, w15, #8, #8",
+        "bfi w20, w20, #16, #16",
+        "neg w21, w5",
+        "ror w20, w20, w21",
+        "bfxil x15, x20, #0, #8",
+        "eor x21, x20, #0x1",
+        "rmif x21, #63, #nzCv",
+        "eor w20, w20, w20, lsr #7",
+        "rmif x20, #0, #nzcV",
+        "and w20, w15, w14",
+        "bfxil x15, x20, #0, #8",
+        "orr w20, w12, w14",
+        "bfxil x12, x20, #0, #8",
+        "mov w20, #0x31",
+        "add x21, x8, x11",
+        "ldrb w21, [x21, #79]",
+        "lsl w0, w21, #24",
+        "cmp w0, w20, lsl #24",
+        "uxtb w5, w12",
+        "uxtb w12, w15",
+        "csel w12, w5, w12, eq",
+        "add x4, x4, #0x1 (1)",
+        "strb w12, [x9, x13, sxtx]",
+        "mvn w27, w11",
+        "subs x26, x11, #0x1 (1)",
+        "cfinv",
+        "mov x11, x26"
+      ]
+    },
     "pcmpistri xmm0, xmm1, 0_0_00_11_01b": {
       "ExpectedInstructionCount": 41,
       "Comment": [