From f4744f1e79dc797752ef32898e8abaa1b4f64cf2 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sun, 27 Oct 2024 17:44:57 -0700
Subject: [PATCH] IR: Change VStoreNonTemporalPair to use IR::OpSize

---
 FEXCore/Source/Interface/IR/IR.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index a93be97d6..d17671c83 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -740,7 +740,7 @@
           "RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i256Bit"
         ]
       },
-      "VStoreNonTemporalPair u8:#RegisterSize, FPR:$ValueLow, FPR:$ValueHigh, GPR:$Addr, i8:$Offset": {
+      "VStoreNonTemporalPair OpSize:#RegisterSize, FPR:$ValueLow, FPR:$ValueHigh, GPR:$Addr, i8:$Offset": {
         "Desc": ["Does a non-temporal memory store of two vector registers.",
                  "Matches arm64 stnp semantics.",
                  "Specifically weak-memory model ordered to match x86 non-temporal stores."