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IR: Change PCLMUL to use IR::OpSize

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Ryan Houdek 2024-10-28 01:40:21 -07:00
parent d26d9e7e03
commit f4e930262f
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2 changed files with 2 additions and 2 deletions
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2
FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
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@ -414,7 +414,7 @@ void OpDispatchBuilder::PCLMULQDQOp(OpcodeArgs) {
}
void OpDispatchBuilder::VPCLMULQDQOp(OpcodeArgs) {
const auto DstSize = GetDstSize(Op);
const auto DstSize = OpSizeFromDst(Op);
Ref Src1 = LoadSource(FPRClass, Op, Op->Src[0], Op->Flags);
Ref Src2 = LoadSource(FPRClass, Op, Op->Src[1], Op->Flags);

2
FEXCore/Source/Interface/IR/IR.json
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@ -2652,7 +2652,7 @@
],
"DestSize": "4"
},
"FPR = PCLMUL u8:#RegisterSize, FPR:$Src1, FPR:$Src2, u8:$Selector": {
"FPR = PCLMUL OpSize:#RegisterSize, FPR:$Src1, FPR:$Src2, u8:$Selector": {
"Desc": [
"Performs carryless multiplication of 64-bit elements depending on the selector.",
"Selector = 0b00000000: Uses low 64-bit elements from both input vectors",