mirror of
https://github.com/FEX-Emu/FEX.git
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Merge pull request #3352 from Sonicadvance1/remove_irloader
Removes IRLoader, unittests, and public interface
This commit is contained in:
Ryan Houdek
GitHub
commit
f785b38e4d
12
.github/workflows/ccpp.yml
vendored
12
.github/workflows/ccpp.yml
vendored
@ -77,18 +77,6 @@ jobs:
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shell: bash
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run: cmake --build . --config $BUILD_TYPE --target install
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- name: IR Tests
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working-directory: ${{runner.workspace}}/build
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shell: bash
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# Execute the unit tests
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run: cmake --build . --config $BUILD_TYPE --target ir_tests
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- name: IR Test Results move
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if: ${{ always() }}
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shell: bash
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working-directory: ${{runner.workspace}}/build
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run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
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- name: gcc target tests 64
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working-directory: ${{runner.workspace}}/build
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shell: bash
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12
.github/workflows/glibc_fault.yml
vendored
12
.github/workflows/glibc_fault.yml
vendored
@ -84,18 +84,6 @@ jobs:
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shell: bash
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run: cmake --build . --config $BUILD_TYPE --target install
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- name: IR Tests
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working-directory: ${{runner.workspace}}/build
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shell: bash
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# Execute the unit tests
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run: cmake --build . --config $BUILD_TYPE --target ir_tests
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- name: IR Test Results move
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if: ${{ always() }}
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shell: bash
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working-directory: ${{runner.workspace}}/build
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run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
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- name: gcc target tests 64
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working-directory: ${{runner.workspace}}/build
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shell: bash
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12
.github/workflows/vixl_simulator.yml
vendored
12
.github/workflows/vixl_simulator.yml
vendored
@ -100,18 +100,6 @@ jobs:
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working-directory: ${{runner.workspace}}/build
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run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_ASM128bit.log || true
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- name: IR Tests
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working-directory: ${{runner.workspace}}/build
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shell: bash
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# Execute the unit tests
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run: cmake --build . --config $BUILD_TYPE --target ir_tests
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- name: IR Test Results move
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if: ${{ always() }}
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shell: bash
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working-directory: ${{runner.workspace}}/build
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run: mv ${{runner.workspace}}/build/Testing/Temporary/LastTest.log ${{runner.workspace}}/build/Testing/Temporary/LastTest_IR.log || true
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- name: Truncate test results
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if: ${{ always() }}
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shell: bash
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@ -171,7 +171,7 @@ namespace FEXCore::Context {
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void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) override;
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// returns false if a handler was already registered
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CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr) override;
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CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr);
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void AppendThunkDefinitions(fextl::vector<FEXCore::IR::ThunkDefinition> const& Definitions) override;
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@ -20,6 +20,8 @@ $end_info$
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#include "Interface/Core/Dispatcher/Dispatcher.h"
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#include "Interface/Core/X86Tables/X86Tables.h"
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#include "Interface/HLE/Thunks/Thunks.h"
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#include "Interface/IR/IR.h"
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/Passes/RegisterAllocationPass.h"
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#include "Interface/IR/Passes.h"
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#include "Interface/IR/PassManager.h"
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@ -38,7 +40,6 @@ $end_info$
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#include <FEXCore/HLE/SourcecodeResolver.h>
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#include <FEXCore/HLE/Linux/ThreadManagement.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/IR/RegisterAllocationData.h>
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#include <FEXCore/Utils/Allocator.h>
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@ -11,6 +11,7 @@ $end_info$
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#include "Interface/Context/Context.h"
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#include "Interface/Core/OpcodeDispatcher.h"
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#include "Interface/Core/X86Tables/X86Tables.h"
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#include "Interface/IR/IREmitter.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Core/Context.h>
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@ -18,7 +19,6 @@ $end_info$
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#include <FEXCore/Core/X86Enums.h>
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#include <FEXCore/HLE/SyscallHandler.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/Utils/EnumUtils.h>
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#include <FEXCore/Utils/LogManager.h>
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@ -4,13 +4,13 @@
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#include "Interface/Core/Frontend.h"
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#include "Interface/Core/X86Tables/X86Tables.h"
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#include "Interface/Context/Context.h"
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#include "Interface/IR/IREmitter.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Core/Context.h>
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#include <FEXCore/Core/X86Enums.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/Utils/MathUtils.h>
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@ -8,7 +8,6 @@ $end_info$
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#include "Interface/Core/X86Tables/X86Tables.h"
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/Utils/LogManager.h>
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#include "Interface/Core/OpcodeDispatcher.h"
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@ -14,7 +14,6 @@ $end_info$
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#include <FEXCore/Utils/EnumUtils.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/Utils/FPState.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <stddef.h>
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#include <stdint.h>
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@ -13,7 +13,6 @@ $end_info$
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#include <FEXCore/Core/X86Enums.h>
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#include <FEXCore/Utils/EnumUtils.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <stddef.h>
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#include <stdint.h>
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@ -6,12 +6,13 @@ tags: glue|thunks
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$end_info$
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*/
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#include "Interface/IR/IREmitter.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/Debug/InternalThreadState.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/Utils/CompilerDefs.h>
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#include <FEXCore/fextl/set.h>
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#include <FEXCore/fextl/string.h>
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@ -231,7 +232,7 @@ namespace FEXCore {
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LogMan::Msg::DFmt("Thunks: Adding guest trampoline from address {:#x} to guest function {:#x}",
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args->original_callee, args->target_addr);
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auto Result = Thread->CTX->AddCustomIREntrypoint(
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auto Result = CTX->AddCustomIREntrypoint(
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args->original_callee,
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[CTX, GuestThunkEntrypoint = args->target_addr](uintptr_t Entrypoint, FEXCore::IR::IREmitter *emit) {
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auto IRHeader = emit->_IRHeader(emit->Invalid(), Entrypoint, 0, 0);
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19
FEXCore/Source/Interface/IR/IR.h
Normal file
19
FEXCore/Source/Interface/IR/IR.h
Normal file
@ -0,0 +1,19 @@
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// SPDX-License-Identifier: MIT
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#pragma once
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#include <FEXCore/Utils/ThreadPoolAllocator.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/fextl/memory.h>
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#include <FEXCore/fextl/sstream.h>
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namespace FEXCore::IR {
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class RegisterAllocationData;
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class IRListView;
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class IREmitter;
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void Dump(fextl::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData);
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fextl::unique_ptr<IREmitter> Parse(FEXCore::Utils::IntrusivePooledAllocator &ThreadAllocator, fextl::stringstream &MapsStream);
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}
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@ -6,8 +6,9 @@ tags: ir|emitter
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$end_info$
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*/
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#include "Interface/IR/IREmitter.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/Utils/EnumUtils.h>
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#include <FEXCore/Utils/LogManager.h>
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@ -6,9 +6,9 @@ tags: ir|parser
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$end_info$
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*/
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#include "Interface/IR/IREmitter.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/Utils/StringUtils.h>
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#include <FEXCore/fextl/sstream.h>
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@ -13,10 +13,10 @@ $end_info$
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#include "aarch64/disasm-aarch64.h"
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#include "aarch64/assembler-aarch64.h"
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/PassManager.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/Utils/Profiler.h>
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@ -5,10 +5,10 @@ tags: ir|opts
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$end_info$
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*/
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/PassManager.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/Utils/Profiler.h>
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@ -6,12 +6,12 @@ desc: Transforms ContextLoad/Store to temporaries, similar to mem2reg
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$end_info$
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*/
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/Passes.h"
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#include "Interface/IR/PassManager.h"
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IREmitter.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/Utils/EnumOperators.h>
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#include <FEXCore/Utils/LogManager.h>
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@ -6,11 +6,11 @@ desc: Cross block store-after-store elimination
|
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$end_info$
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*/
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/PassManager.h"
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|
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#include <FEXCore/Core/CoreState.h>
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#include <FEXCore/IR/IR.h>
|
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#include <FEXCore/IR/IREmitter.h>
|
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#include <FEXCore/IR/IntrusiveIRList.h>
|
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/Utils/Profiler.h>
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@ -6,11 +6,11 @@ desc: Sorts the ssa storage in memory, needed for RA and others
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$end_info$
|
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*/
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|
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#include "Interface/IR/IREmitter.h"
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#include "Interface/IR/PassManager.h"
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#include "Interface/Core/OpcodeDispatcher.h"
|
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|
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#include <FEXCore/IR/IR.h>
|
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#include <FEXCore/IR/IREmitter.h>
|
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#include <FEXCore/IR/IntrusiveIRList.h>
|
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#include <FEXCore/Utils/LogManager.h>
|
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#include <FEXCore/Utils/MathUtils.h>
|
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|
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@ -6,6 +6,8 @@ desc: Prints IR
|
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$end_info$
|
||||
*/
|
||||
|
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#include "Interface/IR/IR.h"
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/PassManager.h"
|
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#include "Interface/IR/Passes/RegisterAllocationPass.h"
|
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#include "Interface/Core/OpcodeDispatcher.h"
|
||||
|
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@ -6,12 +6,13 @@ desc: Sanity checking pass
|
||||
$end_info$
|
||||
*/
|
||||
|
||||
#include "Interface/IR/IR.h"
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/PassManager.h"
|
||||
#include "Interface/IR/Passes/IRValidation.h"
|
||||
#include "Interface/IR/Passes/RegisterAllocationPass.h"
|
||||
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/IR/RegisterAllocationData.h>
|
||||
#include <FEXCore/Utils/LogManager.h>
|
||||
|
||||
@ -7,10 +7,10 @@ $end_info$
|
||||
*/
|
||||
|
||||
#include "Interface/Core/CPUID.h"
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/PassManager.h"
|
||||
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/HLE/SyscallHandler.h>
|
||||
#include <FEXCore/Utils/Profiler.h>
|
||||
|
||||
@ -6,9 +6,9 @@ desc: Long divide elimination pass
|
||||
$end_info$
|
||||
*/
|
||||
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/PassManager.h"
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/Utils/Profiler.h>
|
||||
|
||||
|
||||
@ -1,10 +1,12 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
|
||||
#include "Interface/IR/IR.h"
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/PassManager.h"
|
||||
#include "Interface/IR/Passes/IRValidation.h"
|
||||
#include "Interface/IR/Passes/RegisterAllocationPass.h"
|
||||
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/IR/RegisterAllocationData.h>
|
||||
#include <FEXCore/Utils/Profiler.h>
|
||||
|
||||
@ -6,8 +6,9 @@ desc: This is not used right now, possibly broken
|
||||
$end_info$
|
||||
*/
|
||||
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/Utils/Profiler.h>
|
||||
|
||||
|
||||
@ -7,10 +7,10 @@ $end_info$
|
||||
|
||||
#include "Interface/IR/Passes/RegisterAllocationPass.h"
|
||||
#include "FEXCore/Core/X86Enums.h"
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/Passes.h"
|
||||
#include <FEXCore/Core/CoreState.h>
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/IR/RegisterAllocationData.h>
|
||||
#include <FEXCore/Utils/BitUtils.h>
|
||||
|
||||
@ -6,10 +6,11 @@ desc: Sanity Checking
|
||||
$end_info$
|
||||
*/
|
||||
|
||||
#include "Interface/IR/IR.h"
|
||||
#include "Interface/IR/IREmitter.h"
|
||||
#include "Interface/IR/PassManager.h"
|
||||
|
||||
#include <FEXCore/IR/IR.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/IR/IntrusiveIRList.h>
|
||||
#include <FEXCore/Utils/LogManager.h>
|
||||
#include <FEXCore/Utils/Profiler.h>
|
||||
|
||||
@ -232,7 +232,6 @@ namespace FEXCore::Context {
|
||||
FEX_DEFAULT_VISIBILITY virtual void MarkMemoryShared(FEXCore::Core::InternalThreadState *Thread) = 0;
|
||||
|
||||
FEX_DEFAULT_VISIBILITY virtual void ConfigureAOTGen(FEXCore::Core::InternalThreadState *Thread, fextl::set<uint64_t> *ExternalBranches, uint64_t SectionMaxAddress) = 0;
|
||||
FEX_DEFAULT_VISIBILITY virtual CustomIRResult AddCustomIREntrypoint(uintptr_t Entrypoint, CustomIREntrypointHandler Handler, void *Creator = nullptr, void *Data = nullptr) = 0;
|
||||
|
||||
/**
|
||||
* @brief Allows the frontend to register its own thunk handlers independent of what is controlled in the backend.
|
||||
|
||||
@ -660,9 +660,6 @@ public:
|
||||
class IRListView;
|
||||
class IREmitter;
|
||||
|
||||
FEX_DEFAULT_VISIBILITY void Dump(fextl::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData);
|
||||
FEX_DEFAULT_VISIBILITY fextl::unique_ptr<IREmitter> Parse(FEXCore::Utils::IntrusivePooledAllocator &ThreadAllocator, fextl::stringstream &MapsStream);
|
||||
|
||||
template<typename Type>
|
||||
inline NodeID NodeWrapperBase<Type>::ID() const {
|
||||
return NodeID(NodeOffset / sizeof(IR::OrderedNode));
|
||||
|
||||
@ -20,10 +20,6 @@ if (NOT MINGW_BUILD)
|
||||
add_subdirectory(CodeSizeValidation/)
|
||||
add_subdirectory(LinuxEmulation/)
|
||||
|
||||
if (BUILD_TESTS)
|
||||
add_subdirectory(IRLoader/)
|
||||
endif()
|
||||
|
||||
add_subdirectory(FEXLoader/)
|
||||
endif()
|
||||
|
||||
|
||||
@ -1,23 +0,0 @@
|
||||
list(APPEND LIBS FEXCore Common)
|
||||
|
||||
add_executable(IRLoader
|
||||
IRLoader.cpp
|
||||
)
|
||||
|
||||
if (ENABLE_VIXL_SIMULATOR)
|
||||
target_compile_definitions(IRLoader PRIVATE "-DVIXL_SIMULATOR=1")
|
||||
endif()
|
||||
|
||||
target_include_directories(IRLoader
|
||||
PRIVATE
|
||||
${CMAKE_CURRENT_SOURCE_DIR}/Source/
|
||||
${CMAKE_BINARY_DIR}/generated
|
||||
)
|
||||
target_link_libraries(IRLoader
|
||||
PRIVATE
|
||||
${LIBS}
|
||||
LinuxEmulation
|
||||
CommonTools
|
||||
${PTHREAD_LIB}
|
||||
fmt::fmt
|
||||
)
|
||||
@ -1,229 +0,0 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
/*
|
||||
$info$
|
||||
tags: Bin|IRLoader
|
||||
desc: Used to run IR Tests
|
||||
$end_info$
|
||||
*/
|
||||
|
||||
#include "Common/ArgumentLoader.h"
|
||||
#include "LinuxSyscalls/SignalDelegator.h"
|
||||
|
||||
#include <FEXCore/Config/Config.h>
|
||||
#include <FEXCore/Core/CodeLoader.h>
|
||||
#include <FEXCore/Core/Context.h>
|
||||
#include <FEXCore/Core/CoreState.h>
|
||||
#include <FEXCore/Core/HostFeatures.h>
|
||||
#include <FEXCore/Utils/Allocator.h>
|
||||
#include <FEXCore/Utils/EnumUtils.h>
|
||||
#include <FEXCore/Utils/FileLoading.h>
|
||||
#include <FEXCore/Utils/LogManager.h>
|
||||
#include <FEXCore/HLE/SyscallHandler.h>
|
||||
#include <FEXCore/IR/IREmitter.h>
|
||||
#include <FEXCore/fextl/fmt.h>
|
||||
#include <FEXCore/fextl/sstream.h>
|
||||
|
||||
#include <csetjmp>
|
||||
#include <functional>
|
||||
#include <memory>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/mman.h>
|
||||
#include <vector>
|
||||
|
||||
#include "HarnessHelpers.h"
|
||||
|
||||
namespace FEXCore::Context {
|
||||
class Context;
|
||||
}
|
||||
|
||||
void MsgHandler(LogMan::DebugLevels Level, char const *Message)
|
||||
{
|
||||
fextl::fmt::print("[{}] {}\n", LogMan::DebugLevelStr(Level), Message);
|
||||
fflush(stdout);
|
||||
}
|
||||
|
||||
void AssertHandler(char const *Message)
|
||||
{
|
||||
fextl::fmt::print("[ASSERT] {}\n", Message);
|
||||
fflush(stdout);
|
||||
}
|
||||
|
||||
using namespace FEXCore::IR;
|
||||
class IRCodeLoader final {
|
||||
public:
|
||||
IRCodeLoader(fextl::string const &Filename, fextl::string const &ConfigFilename) {
|
||||
Config.Init(ConfigFilename);
|
||||
|
||||
fextl::string IRFile;
|
||||
if (!FEXCore::FileLoading::LoadFile(IRFile, Filename)) {
|
||||
LogMan::Msg::EFmt("Couldn't open IR file '{}'", Filename);
|
||||
return;
|
||||
}
|
||||
fextl::stringstream IRStream(IRFile);
|
||||
ParsedCode = FEXCore::IR::Parse(Allocator, IRStream);
|
||||
|
||||
if (ParsedCode) {
|
||||
EntryRIP = 0x40000;
|
||||
|
||||
fextl::stringstream out;
|
||||
auto IR = ParsedCode->ViewIR();
|
||||
FEXCore::IR::Dump(&out, &IR, nullptr);
|
||||
fextl::fmt::print("IR:\n{}\n@@@@@\n", out.str());
|
||||
|
||||
for (auto &[region, size] : Config.GetMemoryRegions()) {
|
||||
FEXCore::Allocator::mmap(reinterpret_cast<void *>(region), size, PROT_READ | PROT_WRITE, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
|
||||
}
|
||||
|
||||
Config.LoadMemory();
|
||||
}
|
||||
}
|
||||
|
||||
bool LoadIR(FEXCore::Context::Context *CTX) const {
|
||||
if (!ParsedCode) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return !!CTX->AddCustomIREntrypoint(EntryRIP, [ParsedCodePtr = ParsedCode.get()](uintptr_t Entrypoint, FEXCore::IR::IREmitter *emit) {
|
||||
emit->CopyData(*ParsedCodePtr);
|
||||
});
|
||||
}
|
||||
|
||||
bool CompareStates(FEXCore::Core::CPUState const *State, bool SupportsAVX) {
|
||||
return Config.CompareStates(State, nullptr, SupportsAVX);
|
||||
}
|
||||
|
||||
uint64_t GetStackPointer()
|
||||
{
|
||||
return reinterpret_cast<uint64_t>(FEXCore::Allocator::mmap(nullptr, STACK_SIZE, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0));
|
||||
}
|
||||
|
||||
uint64_t DefaultRIP() const
|
||||
{
|
||||
return EntryRIP;
|
||||
}
|
||||
|
||||
bool RequiresAVX() const {
|
||||
return Config.RequiresAVX();
|
||||
}
|
||||
|
||||
private:
|
||||
uint64_t EntryRIP{};
|
||||
fextl::unique_ptr<IREmitter> ParsedCode;
|
||||
|
||||
FEXCore::Utils::PooledAllocatorMalloc Allocator;
|
||||
FEX::HarnessHelper::ConfigLoader Config;
|
||||
constexpr static uint64_t STACK_SIZE = 8 * 1024 * 1024;
|
||||
};
|
||||
|
||||
class DummySyscallHandler: public FEXCore::HLE::SyscallHandler, public FEXCore::Allocator::FEXAllocOperators {
|
||||
public:
|
||||
uint64_t HandleSyscall(FEXCore::Core::CpuStateFrame *Frame, FEXCore::HLE::SyscallArguments *Args) override {
|
||||
LOGMAN_MSG_A_FMT("Syscalls not implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
FEXCore::HLE::SyscallABI GetSyscallABI(uint64_t Syscall) override {
|
||||
LOGMAN_MSG_A_FMT("Syscalls not implemented");
|
||||
return {0, false, 0 };
|
||||
}
|
||||
|
||||
// These are no-ops implementations of the SyscallHandler API
|
||||
FEXCore::HLE::AOTIRCacheEntryLookupResult LookupAOTIRCacheEntry(FEXCore::Core::InternalThreadState *Thread, uint64_t GuestAddr) override {
|
||||
return {0, 0};
|
||||
}
|
||||
};
|
||||
|
||||
int main(int argc, char **argv, char **const envp)
|
||||
{
|
||||
FEXCore::Allocator::GLIBCScopedFault GLIBFaultScope;
|
||||
LogMan::Throw::InstallHandler(AssertHandler);
|
||||
LogMan::Msg::InstallHandler(MsgHandler);
|
||||
|
||||
FEXCore::Config::Initialize();
|
||||
FEXCore::Config::AddLayer(fextl::make_unique<FEX::ArgLoader::ArgLoader>(argc, argv));
|
||||
FEXCore::Config::AddLayer(FEX::Config::CreateEnvironmentLayer(envp));
|
||||
FEXCore::Config::Load();
|
||||
// Ensure the IRLoader runs in 64-bit mode.
|
||||
// This is to ensure that static register allocation in the JIT
|
||||
// is configured correctly for accesses to the top 8 GPRs and 8 XMM registers.
|
||||
FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_IS64BIT_MODE, "1");
|
||||
#ifdef VIXL_SIMULATOR
|
||||
// If running under the vixl simulator, ensure that indirect runtime calls are enabled.
|
||||
FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_DISABLE_VIXL_INDIRECT_RUNTIME_CALLS, "0");
|
||||
#endif
|
||||
|
||||
auto Args = FEX::ArgLoader::Get();
|
||||
auto ParsedArgs = FEX::ArgLoader::GetParsedArgs();
|
||||
|
||||
LOGMAN_THROW_A_FMT(Args.size() > 1, "Not enough arguments");
|
||||
|
||||
FEXCore::Context::InitializeStaticTables();
|
||||
auto CTX = FEXCore::Context::Context::CreateNewContext();
|
||||
|
||||
auto SignalDelegation = FEX::HLE::CreateSignalDelegator(CTX.get(), {});
|
||||
|
||||
CTX->SetSignalDelegator(SignalDelegation.get());
|
||||
CTX->SetSyscallHandler(new DummySyscallHandler());
|
||||
|
||||
IRCodeLoader Loader(Args[0], Args[1]);
|
||||
|
||||
// Skip tests that require AVX on hosts that don't support it.
|
||||
const bool SupportsAVX = CTX->GetHostFeatures().SupportsAVX;
|
||||
if (!SupportsAVX && Loader.RequiresAVX()) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int Return{};
|
||||
|
||||
if (Loader.LoadIR(CTX.get()))
|
||||
{
|
||||
if (!CTX->InitCore()) {
|
||||
return -1;
|
||||
}
|
||||
auto ParentThread = CTX->CreateThread(Loader.DefaultRIP(), Loader.GetStackPointer());
|
||||
|
||||
auto ShutdownReason = FEXCore::Context::ExitReason::EXIT_SHUTDOWN;
|
||||
|
||||
// There might already be an exit handler, leave it installed
|
||||
if (!CTX->GetExitHandler())
|
||||
{
|
||||
CTX->SetExitHandler([&](uint64_t thread, FEXCore::Context::ExitReason reason) {
|
||||
if (reason != FEXCore::Context::ExitReason::EXIT_DEBUG)
|
||||
{
|
||||
ShutdownReason = reason;
|
||||
}
|
||||
});
|
||||
}
|
||||
|
||||
jmp_buf LongJump{};
|
||||
int LongJumpVal{};
|
||||
|
||||
SignalDelegation->RegisterFrontendHostSignalHandler(SIGSEGV, [&LongJump](FEXCore::Core::InternalThreadState *Thread, int Signal, void *info, void *ucontext) {
|
||||
longjmp(LongJump, 1);
|
||||
return false;
|
||||
}, true);
|
||||
|
||||
LongJumpVal = setjmp(LongJump);
|
||||
if (!LongJumpVal) {
|
||||
CTX->RunUntilExit(ParentThread);
|
||||
}
|
||||
|
||||
LogMan::Msg::DFmt("Reason we left VM: {}", FEXCore::ToUnderlying(ShutdownReason));
|
||||
|
||||
// Just re-use compare state. It also checks against the expected values in config.
|
||||
const bool Passed = Loader.CompareStates(&ParentThread->CurrentFrame->State, SupportsAVX);
|
||||
|
||||
LogMan::Msg::IFmt("Passed? {}\n", Passed ? "Yes" : "No");
|
||||
|
||||
Return = Passed ? 0 : -1;
|
||||
CTX->DestroyThread(ParentThread);
|
||||
}
|
||||
else
|
||||
{
|
||||
LogMan::Msg::EFmt("Couldn't load IR");
|
||||
Return = -1;
|
||||
}
|
||||
|
||||
return Return;
|
||||
}
|
||||
@ -1,6 +1,5 @@
|
||||
if (NOT MINGW_BUILD)
|
||||
add_subdirectory(APITests/)
|
||||
add_subdirectory(IR/)
|
||||
add_subdirectory(POSIX/)
|
||||
add_subdirectory(gvisor-tests/)
|
||||
add_subdirectory(gcc-target-tests-32/)
|
||||
|
||||
@ -1,23 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "RAX": "0xddccbbaa"
|
||||
; },
|
||||
; "MemoryRegions": {
|
||||
; "0x100000": "4096"
|
||||
; },
|
||||
; "MemoryData": {
|
||||
; "0x100000": "AA BB CC DD"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %start, %end, %1
|
||||
(%start i0) BeginBlock %2
|
||||
%Addr i64 = Constant #0x100000
|
||||
%Val i32 = LoadMem GPR, #8, %Addr i64, %Invalid, #8, SXTX, #1
|
||||
(%Store i64) StoreRegister %Val i64, #0, #8, GPR, GPRFixed, #8
|
||||
(%brk i0) Break {0.11.0.128}
|
||||
(%end i0) EndBlock %2
|
||||
|
||||
@ -1,42 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "RAX": "0xffffffffffffff80",
|
||||
; "RBX": "0xffffffffffff8080",
|
||||
; "RCX": "0xffffffff80008080",
|
||||
; "RDX": "0xfffffffffffffff0",
|
||||
; "RSI": "0xfffffffffffffffc"
|
||||
; },
|
||||
; "MemoryRegions": {
|
||||
; "0x1000000": "4096"
|
||||
; },
|
||||
; "MemoryData": {
|
||||
; "0x1000000": "0x0000000080008080",
|
||||
; "0x1000008": "0x0000000000000030"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %start, %end, %1
|
||||
(%start i0) BeginBlock %2
|
||||
%Addr1 i64 = Constant #0x1000000
|
||||
%Val i64 = LoadMem GPR, #8, %Addr1 i64, %Invalid, #8, SXTX, #1
|
||||
; Test aligned special cases
|
||||
%Res1 i64 = Sbfe i64, #0x8, #0x0, %Val
|
||||
(%Store1 i64) StoreRegister %Res1 i64, #0, #8, GPR, GPRFixed, #8
|
||||
%Res2 i64 = Sbfe i64, #0x10, #0x0, %Val
|
||||
(%Store2 i64) StoreRegister %Res2 i64, #0, #0x20, GPR, GPRFixed, #8
|
||||
%Res3 i64 = Sbfe i64, #0x20, #0x0, %Val
|
||||
(%Store3 i64) StoreRegister %Res3 i64, #0, #0x10, GPR, GPRFixed, #8
|
||||
%Addr2 i64 = Constant #0x1000008
|
||||
; Test non special width
|
||||
%Val2 i64 = LoadMem GPR, #8, %Addr2 i64, %Invalid, #8, SXTX, #1
|
||||
|
||||
%Res4 i64 = Sbfe i64, #0x6, #0x0, %Val2
|
||||
(%Store4 i64) StoreRegister %Res4 i64, #0, #0x18, GPR, GPRFixed, #8
|
||||
; Test with + shift
|
||||
%Res5 i64 = Sbfe i64, #0x4, #0x2, %Val2
|
||||
(%Store5 i64) StoreRegister %Res5 i64, #0, #0x38, GPR, GPRFixed, #8
|
||||
(%brk i0) Break {0.11.0.128}
|
||||
(%end i0) EndBlock %2
|
||||
@ -1,15 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "RAX": "0x4142434445464748"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %6, %8, %3
|
||||
(%6 i0) BeginBlock %2
|
||||
%Value i64 = Constant #0x4142434445464748
|
||||
(%Store i64) StoreRegister %Value i64, #0, #0x8, GPR, GPRFixed, #8
|
||||
(%7 i0) Break {0.11.0.128}
|
||||
(%8 i0) EndBlock %2
|
||||
@ -1,78 +0,0 @@
|
||||
|
||||
# Careful. Globbing can't see changes to the contents of files
|
||||
# Need to do a fresh clean to see changes
|
||||
file(GLOB_RECURSE IR_SOURCES CONFIGURE_DEPENDS *.ir)
|
||||
|
||||
set(IR_DEPENDS "")
|
||||
foreach(IR_SRC ${IR_SOURCES})
|
||||
get_filename_component(IR_NAME ${IR_SRC} NAME)
|
||||
|
||||
# Generate a temporary file
|
||||
set(TMP_FILE "${CMAKE_CURRENT_BINARY_DIR}/${IR_TMP}")
|
||||
|
||||
set(OUTPUT_CONFIG_NAME "${IR_NAME}.config.bin")
|
||||
|
||||
add_custom_command(OUTPUT ${OUTPUT_CONFIG_NAME}
|
||||
DEPENDS "${IR_SRC}"
|
||||
DEPENDS "${CMAKE_SOURCE_DIR}/Scripts/json_ir_config_parse.py"
|
||||
DEPENDS "${CMAKE_SOURCE_DIR}/Scripts/json_config_parse.py"
|
||||
COMMAND "python3" ARGS "${CMAKE_SOURCE_DIR}/Scripts/json_ir_config_parse.py" "${IR_SRC}" "${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_CONFIG_NAME}")
|
||||
|
||||
list(APPEND IR_DEPENDS "${OUTPUT_CONFIG_NAME}")
|
||||
|
||||
# Since we pass in raw IR, we don't need to worry about various IR gen options
|
||||
set(TEST_ARGS
|
||||
"--no-silent -c irjit -n 500" "ir_jit" "jit"
|
||||
)
|
||||
|
||||
set (RUNNER_DISABLED "${CMAKE_SOURCE_DIR}/unittests/ASM/Disabled_Tests")
|
||||
if (DEFINED ENV{runner_label})
|
||||
set (RUNNER_DISABLED "${CMAKE_SOURCE_DIR}/unittests/ASM/Disabled_Tests_$ENV{runner_label}")
|
||||
endif()
|
||||
|
||||
list(LENGTH TEST_ARGS ARG_COUNT)
|
||||
math(EXPR ARG_COUNT "${ARG_COUNT}-1")
|
||||
foreach(Index RANGE 0 ${ARG_COUNT} 3)
|
||||
math(EXPR TEST_NAME_INDEX "${Index}+1")
|
||||
math(EXPR TEST_TYPE_INDEX "${Index}+2")
|
||||
|
||||
list(GET TEST_ARGS ${Index} ARGS)
|
||||
list(GET TEST_ARGS ${TEST_NAME_INDEX} TEST_DESC)
|
||||
list(GET TEST_ARGS ${TEST_TYPE_INDEX} TEST_TYPE)
|
||||
|
||||
set(TEST_NAME "${TEST_DESC}/Test_${IR_NAME}")
|
||||
string(REPLACE " " ";" ARGS_LIST ${ARGS})
|
||||
|
||||
set(TEST_NAME "${TEST_DESC}/Test_${IR_NAME}")
|
||||
string(REPLACE " " ";" ARGS_LIST ${ARGS})
|
||||
add_test(NAME ${TEST_NAME}
|
||||
COMMAND "python3" "${CMAKE_SOURCE_DIR}/Scripts/testharness_runner.py"
|
||||
"${CMAKE_SOURCE_DIR}/unittests/IR/Known_Failures"
|
||||
"${CMAKE_SOURCE_DIR}/unittests/IR/Known_Failures_${TEST_TYPE}"
|
||||
"${CMAKE_SOURCE_DIR}/unittests/IR/Disabled_Tests"
|
||||
"${CMAKE_SOURCE_DIR}/unittests/IR/Disabled_Tests_${TEST_TYPE}"
|
||||
"${RUNNER_DISABLED}"
|
||||
"Test_${IR_NAME}"
|
||||
"${CMAKE_BINARY_DIR}/Bin/IRLoader"
|
||||
${ARGS_LIST} "${IR_SRC}" "${OUTPUT_CONFIG_NAME}")
|
||||
# This will cause the IR tests to fail if it can't find the TestHarness or IRN files
|
||||
# Prety crap way to work around the fact that tests can't have a build dependency in a different directory
|
||||
# Just make sure to independently run `make all` then `make test`
|
||||
set_property(TEST ${TEST_NAME} APPEND PROPERTY DEPENDS "${CMAKE_BINARY_DIR}/Bin/IRLoader")
|
||||
set_property(TEST ${TEST_NAME} APPEND PROPERTY DEPENDS "${IRC_SRC}")
|
||||
set_property(TEST ${TEST_NAME} APPEND PROPERTY DEPENDS "${OUTPUT_CONFIG_NAME}")
|
||||
|
||||
endforeach()
|
||||
endforeach()
|
||||
|
||||
add_custom_target(ir_files ALL
|
||||
DEPENDS "${IR_DEPENDS}")
|
||||
|
||||
execute_process(COMMAND "nproc" OUTPUT_VARIABLE CORES)
|
||||
string(STRIP ${CORES} CORES)
|
||||
|
||||
add_custom_target(
|
||||
ir_tests
|
||||
WORKING_DIRECTORY "${CMAKE_BINARY_DIR}"
|
||||
USES_TERMINAL
|
||||
COMMAND "ctest" "--output-on-failure" "--timeout" "302" "-j${CORES}" "-R" "\.*.ir$$")
|
||||
@ -1,39 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "RAX": "0x00000000fffffff9",
|
||||
; "RBX": "0xfffffffffffffff9",
|
||||
; "RCX": "0x00000000fffffff9",
|
||||
; "RDX": "0xfffffffffffffff9"
|
||||
; },
|
||||
; "MemoryRegions": {
|
||||
; "0x1000000": "4096"
|
||||
; },
|
||||
; "MemoryData": {
|
||||
; "0x1000000": "0xaaaaaaaaaaaaaaa8",
|
||||
; "0x1000010": "51 55 55 55 55 55 55 55"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %6, %12, %1
|
||||
(%6 i0) BeginBlock %2
|
||||
%AddrA i64 = Constant #0x1000000
|
||||
%MemValueA i64 = LoadMem GPR, #8, %AddrA i64, %Invalid, #8, SXTX, #1
|
||||
%AddrB i64 = Constant #0x1000010
|
||||
%MemValueB i64 = LoadMem GPR, #8, %AddrB i64, %Invalid, #8, SXTX, #1
|
||||
%ResultA i32 = Add i32, %MemValueA, %MemValueB
|
||||
%ResultB i64 = Add i64, %MemValueA, %MemValueB
|
||||
|
||||
(%Store i64) StoreRegister %ResultA i64, #0, #0x8, GPR, GPRFixed, #8
|
||||
(%Store i64) StoreRegister %ResultB i64, #0, #0x20, GPR, GPRFixed, #8
|
||||
; Constant optimisable version
|
||||
%ValueC i64 = Constant #0xaaaaaaaaaaaaaaa8
|
||||
%ValueD i64 = Constant #0x5555555555555551
|
||||
%ResultC i32 = Add i32, %ValueC, %ValueD
|
||||
%ResultD i64 = Add i64, %ValueC, %ValueD
|
||||
(%Store i64) StoreRegister %ResultC i64, #0, #0x10, GPR, GPRFixed, #8
|
||||
(%Store i64) StoreRegister %ResultD i64, #0, #0x18, GPR, GPRFixed, #8
|
||||
(%7 i0) Break {0.11.0.128}
|
||||
(%12 i0) EndBlock %2
|
||||
@ -1,65 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "XMM4": ["0x2726252423222120","0x0000000000000000"],
|
||||
; "XMM5": ["0x0000000023222120","0x0000000000000000"],
|
||||
; "XMM6": ["0x0000000000002120","0x0000000000000000"],
|
||||
; "XMM7": ["0x0000000000000020","0x0000000000000000"]
|
||||
; },
|
||||
; "HostFeatures": ["AVX"],
|
||||
; "MemoryRegions": {
|
||||
; "0x1000000": "4096"
|
||||
; },
|
||||
; "MemoryData": {
|
||||
; "0x1000000": "20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f",
|
||||
; "0x1000010": "11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %6, %end, %begin
|
||||
(%begin i0) BeginBlock %2
|
||||
; Clear registers
|
||||
%AddrB i64 = Constant #0x1000010
|
||||
|
||||
%ClearVal i128 = LoadMem FPR, #0x10, %AddrB i64, %Invalid, #0x10, SXTX, #1
|
||||
(%Clear1 i128) StoreRegister %ClearVal i128, #0, #0xc0, FPR, FPRFixed, #0x10
|
||||
(%Clear2 i128) StoreRegister %ClearVal i128, #0, #0xe0, FPR, FPRFixed, #0x10
|
||||
(%Clear3 i128) StoreRegister %ClearVal i128, #0, #0x100, FPR, FPRFixed, #0x10
|
||||
(%Clear4 i128) StoreRegister %ClearVal i128, #0, #0x120, FPR, FPRFixed, #0x10
|
||||
|
||||
%AddrA i64 = Constant #0x1000000
|
||||
|
||||
%MemValueA i128 = LoadMem FPR, #0x10, %AddrA i64, %Invalid, #0x10, SXTX, #1
|
||||
(%Store1 i128) StoreRegister %MemValueA i128, #0, #0xc0, FPR, FPRFixed, #0x10
|
||||
(%Store2 i128) StoreRegister %MemValueA i128, #0, #0xe0, FPR, FPRFixed, #0x10
|
||||
(%Store3 i128) StoreRegister %MemValueA i128, #0, #0x100, FPR, FPRFixed, #0x10
|
||||
|
||||
; Partial insert through load+ins+store
|
||||
%Value i128 = LoadRegister #0, #0x120, FPR, FPRFixed, #0x10
|
||||
%MemInsertA i8v16 = VInsElement #0x10, #1, #0, #0, %Value i128, %MemValueA
|
||||
(%Store4 i128) StoreRegister %MemInsertA i128, #0, #0x120, FPR, FPRFixed, #0x10
|
||||
|
||||
%Value64 i128 = LoadRegister #0, #0xc0, FPR, FPRFixed, #0x10
|
||||
%Truncated64 i64 = VMov #8, %Value64
|
||||
|
||||
%Value32 i128 = LoadRegister #0, #0xe0, FPR, FPRFixed, #0x10
|
||||
%Truncated32 i32 = VMov #4, %Value32
|
||||
|
||||
%Value16 i128 = LoadRegister #0, #0x100, FPR, FPRFixed, #0x10
|
||||
%Truncated16 i16 = VMov #2, %Value16
|
||||
|
||||
%Value8 i128 = LoadRegister #0, #0x120, FPR, FPRFixed, #0x10
|
||||
%Truncated8 i8 = VMov #1, %Value8
|
||||
|
||||
(%Store5 i128) StoreRegister %Truncated64 i128, #0, #0x140, FPR, FPRFixed, #0x10
|
||||
(%Store6 i128) StoreRegister %Truncated32 i128, #0, #0x160, FPR, FPRFixed, #0x10
|
||||
(%Store7 i128) StoreRegister %Truncated16 i128, #0, #0x180, FPR, FPRFixed, #0x10
|
||||
(%Store8 i128) StoreRegister %Truncated8 i128, #0, #0x1a0, FPR, FPRFixed, #0x10
|
||||
(%Store9 i128) StoreRegister %MemValueA i128, #0, #0x1c0, FPR, FPRFixed, #0x10
|
||||
|
||||
(%7 i0) Break {0.11.0.128}
|
||||
(%end i0) EndBlock %2
|
||||
@ -1,36 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "RAX": "0x000000000eca8642",
|
||||
; "RBX": "0x000000010eca8642",
|
||||
; "RCX": "0x000000000eca8642",
|
||||
; "RDX": "0x000000010eca8642"
|
||||
; },
|
||||
; "MemoryRegions": {
|
||||
; "0x1000000": "4096"
|
||||
; },
|
||||
; "MemoryData": {
|
||||
; "0x1000000": "0x87654321",
|
||||
; "0x1000010": "51 55 55 55 55 55 55 55"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %6, %12, %1
|
||||
(%6 i0) BeginBlock %2
|
||||
%AddrA i64 = Constant #0x1000000
|
||||
%MemValueA i32 = LoadMem GPR, #4, %AddrA i64, %Invalid, #4, SXTX, #1
|
||||
%Shift i64 = Constant #0x1
|
||||
%ResultA i32 = Lshl i32, %MemValueA, %Shift
|
||||
%ResultB i64 = Lshl i64, %MemValueA, %Shift
|
||||
(%Store i64) StoreRegister %ResultA i64, #0, #0x8, GPR, GPRFixed, #8
|
||||
(%Store i64) StoreRegister %ResultB i64, #0, #0x20, GPR, GPRFixed, #8
|
||||
; Constant optimisable version
|
||||
%ValueB i64 = Constant #0x87654321
|
||||
%ResultC i32 = Lshl i32, %ValueB, %Shift
|
||||
%ResultD i64 = Lshl i64, %ValueB, %Shift
|
||||
(%Store i64) StoreRegister %ResultC i64, #0, #0x10, GPR, GPRFixed, #8
|
||||
(%Store i64) StoreRegister %ResultD i64, #0, #0x18, GPR, GPRFixed, #8
|
||||
(%7 i0) Break {0.11.0.128}
|
||||
(%12 i0) EndBlock %2
|
||||
@ -1,38 +0,0 @@
|
||||
;%ifdef CONFIG
|
||||
;{
|
||||
; "RegData": {
|
||||
; "RAX": "0x0000000055555557",
|
||||
; "RBX": "0x5555555555555557",
|
||||
; "RCX": "0x0000000055555557",
|
||||
; "RDX": "0x5555555555555557"
|
||||
; },
|
||||
; "MemoryRegions": {
|
||||
; "0x1000000": "4096"
|
||||
; },
|
||||
; "MemoryData": {
|
||||
; "0x1000000": "0xaaaaaaaaaaaaaaa8",
|
||||
; "0x1000010": "51 55 55 55 55 55 55 55"
|
||||
; }
|
||||
;}
|
||||
;%endif
|
||||
|
||||
(%1) IRHeader %2, #0, #0, #0
|
||||
(%2) CodeBlock %6, %12, %1
|
||||
(%Start i0) BeginBlock %2
|
||||
%AddrA i64 = Constant #0x1000000
|
||||
%MemValueA i64 = LoadMem GPR, #8, %AddrA i64, %Invalid, #8, SXTX, #1
|
||||
%AddrB i64 = Constant #0x1000010
|
||||
%MemValueB i64 = LoadMem GPR, #8, %AddrB i64, %Invalid, #8, SXTX, #1
|
||||
%ResultA i32 = Sub i32, %MemValueA, %MemValueB
|
||||
%ResultB i64 = Sub i64, %MemValueA, %MemValueB
|
||||
(%Store i64) StoreRegister %ResultA i64, #0, #0x8, GPR, GPRFixed, #8
|
||||
(%Store i64) StoreRegister %ResultB i64, #0, #0x20, GPR, GPRFixed, #8
|
||||
; Constant optimisable version
|
||||
%ValueC i64 = Constant #0xaaaaaaaaaaaaaaa8
|
||||
%ValueD i64 = Constant #0x5555555555555551
|
||||
%ResultC i32 = Sub i32, %ValueC, %ValueD
|
||||
%ResultD i64 = Sub i64, %ValueC, %ValueD
|
||||
(%Store i64) StoreRegister %ResultC i64, #0, #0x10, GPR, GPRFixed, #8
|
||||
(%Store i64) StoreRegister %ResultD i64, #0, #0x18, GPR, GPRFixed, #8
|
||||
(%7 i0) Break {0.11.0.128}
|
||||
(%12 i0) EndBlock %2
|
||||
Loading…
x
Reference in New Issue
Block a user