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Removes the EndFunction IR Op

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This commit is contained in:
Ryan Houdek 2019-11-04 05:33:53 -08:00 committed by Stefanos Kornilios Mitsis Poiitidis
parent 9218df31c2
commit f8b858e7fc
7 changed files with 14 additions and 21 deletions
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3
Source/Interface/Core/Interpreter/InterpreterCore.cpp
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@ -156,8 +156,7 @@ void InterpreterCore::ExecuteCode(FEXCore::Core::InternalThreadState *Thread) {
Thread->State.State.rip += Op->RIPIncrement; Thread->State.State.rip += Op->RIPIncrement;
break; break;
} }
case IR::OP_EXITFUNCTION: case IR::OP_EXITFUNCTION: {
case IR::OP_ENDFUNCTION: {
Quit = true; Quit = true;
break; break;
} }

3
Source/Interface/Core/JIT/Arm64/JIT.cpp
View File

@ -403,8 +403,7 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
} }
break; break;
} }
case IR::OP_EXITFUNCTION: case IR::OP_EXITFUNCTION: {
case IR::OP_ENDFUNCTION: {
if (SpillSlots) { if (SpillSlots) {
add(sp, sp, SpillSlots * 16); add(sp, sp, SpillSlots * 16);
} }

6
Source/Interface/Core/JIT/x86_64/JIT.cpp
View File

@ -352,8 +352,7 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
} }
break; break;
} }
case IR::OP_EXITFUNCTION: case IR::OP_EXITFUNCTION: {
case IR::OP_ENDFUNCTION: {
if (SpillSlots) { if (SpillSlots) {
add(rsp, SpillSlots * 16); add(rsp, SpillSlots * 16);
} }
@ -382,7 +381,7 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
mov(al, 1); mov(al, 1);
xchg(byte [STATE + offsetof(FEXCore::Core::ThreadState, RunningEvents.ShouldStop)], al); xchg(byte [STATE + offsetof(FEXCore::Core::ThreadState, RunningEvents.ShouldStop)], al);
// This code matches what is in EXITFUNCTION/ENDFUNCTION // This code matches what is in EXITFUNCTION
if (SpillSlots) { if (SpillSlots) {
add(rsp, SpillSlots * 16); add(rsp, SpillSlots * 16);
} }
@ -1684,7 +1683,6 @@ void *JITCore::CompileCode([[maybe_unused]] FEXCore::IR::IRListView<true> const
case IR::OP_BEGINBLOCK: case IR::OP_BEGINBLOCK:
case IR::OP_ENDBLOCK: case IR::OP_ENDBLOCK:
case IR::OP_EXITFUNCTION: case IR::OP_EXITFUNCTION:
case IR::OP_ENDFUNCTION:
case IR::OP_BREAK: case IR::OP_BREAK:
case IR::OP_JUMP: case IR::OP_JUMP:
break; break;

3
Source/Interface/Core/LLVMJIT/LLVMCore.cpp
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@ -803,8 +803,7 @@ void LLVMJITCore::HandleIR(FEXCore::IR::IRListView<true> const *IR, IR::NodeWrap
JITState.IRBuilder->CreateBr(JITCurrentState.ExitBlock); JITState.IRBuilder->CreateBr(JITCurrentState.ExitBlock);
break; break;
} }
case IR::OP_EXITFUNCTION: case IR::OP_EXITFUNCTION: {
case IR::OP_ENDFUNCTION: {
JITState.IRBuilder->CreateBr(JITCurrentState.ExitBlock); JITState.IRBuilder->CreateBr(JITCurrentState.ExitBlock);
break; break;
} }

14
Source/Interface/IR/IR.json
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@ -38,6 +38,13 @@
"Next" "Next"
] ]
}, },
"BeginBlock": {},
"EndBlock": {
"Args": [
"uint64_t", "RIPIncrement"
]
},
"Constant": { "Constant": {
"HasDest": true, "HasDest": true,
"FixedDestSize": "8", "FixedDestSize": "8",
@ -45,12 +52,6 @@
"uint64_t", "Constant" "uint64_t", "Constant"
] ]
}, },
"BeginBlock": {},
"EndBlock": {
"Args": [
"uint64_t", "RIPIncrement"
]
},
"Break": { "Break": {
"Args": [ "Args": [
@ -59,7 +60,6 @@
] ]
}, },
"EndFunction": {},
"ExitFunction": {}, "ExitFunction": {},
"Jump": { "Jump": {

1
Source/Interface/IR/Passes/DeadCodeElimination.cpp
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@ -57,7 +57,6 @@ bool DeadCodeElimination::Run(OpDispatchBuilder *Disp) {
// Control flow // Control flow
case OP_BREAK: case OP_BREAK:
case OP_JUMP: case OP_JUMP:
case OP_ENDFUNCTION:
case OP_EXITFUNCTION: case OP_EXITFUNCTION:
case OP_CONDJUMP: case OP_CONDJUMP:
// Keep // Keep

3
Source/Interface/IR/Passes/IRValidation.cpp
View File

@ -88,8 +88,7 @@ bool IRValidation::Run(OpDispatchBuilder *Disp) {
} }
switch (IROp->Op) { switch (IROp->Op) {
case IR::OP_EXITFUNCTION: case IR::OP_EXITFUNCTION: {
case IR::OP_ENDFUNCTION: {
CurrentBlock->HasExit = true; CurrentBlock->HasExit = true;
break; break;
} }