mirror of
https://github.com/FEX-Emu/FEX.git
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Arm64: Early exit in unaligned handler if not on arm64
NFC, just removes a level of indent
This commit is contained in:
Ryan Houdek
parent
5e706dff64
commit
fa45ec32db
@ -1830,177 +1830,178 @@ HandleUnalignedAccess(FEXCore::Core::InternalThreadState* Thread, UnalignedHandl
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#endif
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constexpr auto NotHandled = std::make_pair(false, 0);
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if constexpr (!is_arm64) {
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return NotHandled;
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}
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if constexpr (is_arm64) {
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uint32_t* PC = (uint32_t*)ProgramCounter;
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uint32_t Instr = PC[0];
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uint32_t* PC = (uint32_t*)ProgramCounter;
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uint32_t Instr = PC[0];
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// 1 = 16bit
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// 2 = 32bit
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// 3 = 64bit
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uint32_t Size = (Instr & 0xC000'0000) >> 30;
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uint32_t AddrReg = (Instr >> 5) & 0x1F;
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uint32_t DataReg = Instr & 0x1F;
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// ParanoidTSO path doesn't modify any code.
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if (HandleType == UnalignedHandlerType::Paranoid) [[unlikely]] {
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if ((Instr & LDAXR_MASK) == LDAR_INST || // LDAR*
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(Instr & LDAXR_MASK) == LDAPR_INST) { // LDAPR*
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if (ArchHelpers::Arm64::HandleAtomicLoad(Instr, GPRs, 0)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & LDAXR_MASK) == STLR_INST) { // STLR*
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if (ArchHelpers::Arm64::HandleAtomicStore(Instr, GPRs, 0)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS STLR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & RCPC2_MASK) == LDAPUR_INST) { // LDAPUR*
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// Extract the 9-bit offset from the instruction
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int32_t Offset = static_cast<int32_t>(Instr) << 11 >> 23;
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if (ArchHelpers::Arm64::HandleAtomicLoad(Instr, GPRs, Offset)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAPUR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & RCPC2_MASK) == STLUR_INST) { // STLUR*
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// Extract the 9-bit offset from the instruction
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int32_t Offset = static_cast<int32_t>(Instr) << 11 >> 23;
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if (ArchHelpers::Arm64::HandleAtomicStore(Instr, GPRs, Offset)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDLUR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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}
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}
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const auto Frame = Thread->CurrentFrame;
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const uint64_t BlockBegin = Frame->State.InlineJITBlockHeader;
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auto InlineHeader = reinterpret_cast<const CPU::CPUBackend::JITCodeHeader*>(BlockBegin);
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auto InlineTail = reinterpret_cast<CPU::CPUBackend::JITCodeTail*>(Frame->State.InlineJITBlockHeader + InlineHeader->OffsetToBlockTail);
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// Lock code mutex during any SIGBUS handling that potentially changes code.
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// Need to be careful to not read any code part-way through modification.
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FEXCore::Utils::SpinWaitLock::UniqueSpinMutex lk(&InlineTail->SpinLockFutex);
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// 1 = 16bit
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// 2 = 32bit
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// 3 = 64bit
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uint32_t Size = (Instr & 0xC000'0000) >> 30;
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uint32_t AddrReg = (Instr >> 5) & 0x1F;
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uint32_t DataReg = Instr & 0x1F;
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// ParanoidTSO path doesn't modify any code.
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if (HandleType == UnalignedHandlerType::Paranoid) [[unlikely]] {
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if ((Instr & LDAXR_MASK) == LDAR_INST || // LDAR*
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(Instr & LDAXR_MASK) == LDAPR_INST) { // LDAPR*
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uint32_t LDR = 0b0011'1000'0111'1111'0110'1000'0000'0000;
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LDR |= Size << 30;
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LDR |= AddrReg << 5;
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LDR |= DataReg;
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PC[0] = LDR;
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[1] = DMB_LD; // Back-patch the half-barrier.
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if (ArchHelpers::Arm64::HandleAtomicLoad(Instr, GPRs, 0)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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ClearICache(&PC[0], 16);
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// With the instruction modified, now execute again.
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return std::make_pair(true, 0);
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} else if ((Instr & LDAXR_MASK) == STLR_INST) { // STLR*
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uint32_t STR = 0b0011'1000'0011'1111'0110'1000'0000'0000;
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STR |= Size << 30;
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STR |= AddrReg << 5;
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STR |= DataReg;
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[-1] = DMB; // Back-patch the half-barrier.
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if (ArchHelpers::Arm64::HandleAtomicStore(Instr, GPRs, 0)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS STLR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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PC[0] = STR;
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ClearICache(&PC[-1], 16);
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// Back up one instruction and have another go
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return std::make_pair(true, -4);
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} else if ((Instr & RCPC2_MASK) == LDAPUR_INST) { // LDAPUR*
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// Extract the 9-bit offset from the instruction
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uint32_t LDUR = 0b0011'1000'0100'0000'0000'0000'0000'0000;
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LDUR |= Size << 30;
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LDUR |= AddrReg << 5;
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LDUR |= DataReg;
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LDUR |= Instr & (0b1'1111'1111 << 9);
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PC[0] = LDUR;
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[1] = DMB_LD; // Back-patch the half-barrier.
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int32_t Offset = static_cast<int32_t>(Instr) << 11 >> 23;
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if (ArchHelpers::Arm64::HandleAtomicLoad(Instr, GPRs, Offset)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAPUR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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ClearICache(&PC[0], 16);
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// With the instruction modified, now execute again.
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return std::make_pair(true, 0);
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} else if ((Instr & RCPC2_MASK) == STLUR_INST) { // STLUR*
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uint32_t STUR = 0b0011'1000'0000'0000'0000'0000'0000'0000;
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STUR |= Size << 30;
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STUR |= AddrReg << 5;
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STUR |= DataReg;
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STUR |= Instr & (0b1'1111'1111 << 9);
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[-1] = DMB; // Back-patch the half-barrier.
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}
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PC[0] = STUR;
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ClearICache(&PC[-1], 16);
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// Back up one instruction and have another go
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return std::make_pair(true, -4);
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} else if ((Instr & ArchHelpers::Arm64::LDAXP_MASK) == ArchHelpers::Arm64::LDAXP_INST) { // LDAXP
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// Should be compare and swap pair only. LDAXP not used elsewhere
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uint64_t BytesToSkip = ArchHelpers::Arm64::HandleCASPAL_ARMv8(Instr, ProgramCounter, GPRs);
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if (BytesToSkip) {
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// Skip this instruction now
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return std::make_pair(true, BytesToSkip);
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} else {
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if (ArchHelpers::Arm64::HandleAtomicVectorStore(Instr, ProgramCounter)) {
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return std::make_pair(true, 0);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAXP: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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}
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} else if ((Instr & ArchHelpers::Arm64::STLXP_MASK) == ArchHelpers::Arm64::STLXP_INST) { // STLXP
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// Should not trigger - middle of an LDAXP/STAXP pair.
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS STLXP: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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} else if ((Instr & ArchHelpers::Arm64::CASPAL_MASK) == ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
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if (ArchHelpers::Arm64::HandleCASPAL(Instr, GPRs)) {
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// Extract the 9-bit offset from the instruction
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int32_t Offset = static_cast<int32_t>(Instr) << 11 >> 23;
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if (ArchHelpers::Arm64::HandleAtomicStore(Instr, GPRs, Offset)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS CASPAL: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & ArchHelpers::Arm64::CASAL_MASK) == ArchHelpers::Arm64::CASAL_INST) { // CASAL
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if (ArchHelpers::Arm64::HandleCASAL(GPRs, Instr)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS CASAL: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & ArchHelpers::Arm64::ATOMIC_MEM_MASK) == ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
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if (ArchHelpers::Arm64::HandleAtomicMemOp(Instr, GPRs)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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uint8_t Op = (PC[0] >> 12) & 0xF;
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}: PC: 0x{:x} Instruction: 0x{:08x}\n", Op, ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & ArchHelpers::Arm64::LDAXR_MASK) == ArchHelpers::Arm64::LDAXR_INST) { // LDAXR*
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uint64_t BytesToSkip = ArchHelpers::Arm64::HandleAtomicLoadstoreExclusive(ProgramCounter, GPRs);
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if (BytesToSkip) {
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// Skip this instruction now
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return std::make_pair(true, BytesToSkip);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAXR: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDLUR*: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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}
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}
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const auto Frame = Thread->CurrentFrame;
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const uint64_t BlockBegin = Frame->State.InlineJITBlockHeader;
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auto InlineHeader = reinterpret_cast<const CPU::CPUBackend::JITCodeHeader*>(BlockBegin);
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auto InlineTail = reinterpret_cast<CPU::CPUBackend::JITCodeTail*>(Frame->State.InlineJITBlockHeader + InlineHeader->OffsetToBlockTail);
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// Lock code mutex during any SIGBUS handling that potentially changes code.
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// Need to be careful to not read any code part-way through modification.
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FEXCore::Utils::SpinWaitLock::UniqueSpinMutex lk(&InlineTail->SpinLockFutex);
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if ((Instr & LDAXR_MASK) == LDAR_INST || // LDAR*
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(Instr & LDAXR_MASK) == LDAPR_INST) { // LDAPR*
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uint32_t LDR = 0b0011'1000'0111'1111'0110'1000'0000'0000;
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LDR |= Size << 30;
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LDR |= AddrReg << 5;
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LDR |= DataReg;
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PC[0] = LDR;
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[1] = DMB_LD; // Back-patch the half-barrier.
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}
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ClearICache(&PC[0], 16);
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// With the instruction modified, now execute again.
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return std::make_pair(true, 0);
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} else if ((Instr & LDAXR_MASK) == STLR_INST) { // STLR*
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uint32_t STR = 0b0011'1000'0011'1111'0110'1000'0000'0000;
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STR |= Size << 30;
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STR |= AddrReg << 5;
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STR |= DataReg;
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[-1] = DMB; // Back-patch the half-barrier.
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}
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PC[0] = STR;
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ClearICache(&PC[-1], 16);
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// Back up one instruction and have another go
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return std::make_pair(true, -4);
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} else if ((Instr & RCPC2_MASK) == LDAPUR_INST) { // LDAPUR*
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// Extract the 9-bit offset from the instruction
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uint32_t LDUR = 0b0011'1000'0100'0000'0000'0000'0000'0000;
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LDUR |= Size << 30;
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LDUR |= AddrReg << 5;
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LDUR |= DataReg;
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LDUR |= Instr & (0b1'1111'1111 << 9);
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PC[0] = LDUR;
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[1] = DMB_LD; // Back-patch the half-barrier.
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}
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ClearICache(&PC[0], 16);
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// With the instruction modified, now execute again.
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return std::make_pair(true, 0);
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} else if ((Instr & RCPC2_MASK) == STLUR_INST) { // STLUR*
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uint32_t STUR = 0b0011'1000'0000'0000'0000'0000'0000'0000;
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STUR |= Size << 30;
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STUR |= AddrReg << 5;
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STUR |= DataReg;
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STUR |= Instr & (0b1'1111'1111 << 9);
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if (HandleType != UnalignedHandlerType::NonAtomic) {
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PC[-1] = DMB; // Back-patch the half-barrier.
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}
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PC[0] = STUR;
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ClearICache(&PC[-1], 16);
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// Back up one instruction and have another go
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return std::make_pair(true, -4);
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} else if ((Instr & ArchHelpers::Arm64::LDAXP_MASK) == ArchHelpers::Arm64::LDAXP_INST) { // LDAXP
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// Should be compare and swap pair only. LDAXP not used elsewhere
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uint64_t BytesToSkip = ArchHelpers::Arm64::HandleCASPAL_ARMv8(Instr, ProgramCounter, GPRs);
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if (BytesToSkip) {
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// Skip this instruction now
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return std::make_pair(true, BytesToSkip);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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if (ArchHelpers::Arm64::HandleAtomicVectorStore(Instr, ProgramCounter)) {
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return std::make_pair(true, 0);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAXP: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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}
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} else if ((Instr & ArchHelpers::Arm64::STLXP_MASK) == ArchHelpers::Arm64::STLXP_INST) { // STLXP
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// Should not trigger - middle of an LDAXP/STAXP pair.
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS STLXP: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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} else if ((Instr & ArchHelpers::Arm64::CASPAL_MASK) == ArchHelpers::Arm64::CASPAL_INST) { // CASPAL
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if (ArchHelpers::Arm64::HandleCASPAL(Instr, GPRs)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS CASPAL: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & ArchHelpers::Arm64::CASAL_MASK) == ArchHelpers::Arm64::CASAL_INST) { // CASAL
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if (ArchHelpers::Arm64::HandleCASAL(GPRs, Instr)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS CASAL: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & ArchHelpers::Arm64::ATOMIC_MEM_MASK) == ArchHelpers::Arm64::ATOMIC_MEM_INST) { // Atomic memory op
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if (ArchHelpers::Arm64::HandleAtomicMemOp(Instr, GPRs)) {
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// Skip this instruction now
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return std::make_pair(true, 4);
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} else {
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uint8_t Op = (PC[0] >> 12) & 0xF;
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS Atomic mem op 0x{:02x}: PC: 0x{:x} Instruction: 0x{:08x}\n", Op, ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else if ((Instr & ArchHelpers::Arm64::LDAXR_MASK) == ArchHelpers::Arm64::LDAXR_INST) { // LDAXR*
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uint64_t BytesToSkip = ArchHelpers::Arm64::HandleAtomicLoadstoreExclusive(ProgramCounter, GPRs);
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if (BytesToSkip) {
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// Skip this instruction now
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return std::make_pair(true, BytesToSkip);
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS LDAXR: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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} else {
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LogMan::Msg::EFmt("Unhandled JIT SIGBUS: PC: 0x{:x} Instruction: 0x{:08x}\n", ProgramCounter, PC[0]);
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return NotHandled;
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}
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return NotHandled;
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}
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