mirror of
https://github.com/FEX-Emu/FEX.git
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Merge pull request #2193 from Sonicadvance1/support_radeon_ioctl_emu
IoctlEmu: Support radeon
This commit is contained in:
Ryan Houdek
GitHub
commit
fc28062052
@ -15,6 +15,7 @@ extern "C" {
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#include "fex-drm/panfrost_drm.h"
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#include "fex-drm/msm_drm.h"
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#include "fex-drm/nouveau_drm.h"
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#include "fex-drm/radeon_drm.h"
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#include "fex-drm/vc4_drm.h"
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#include "fex-drm/v3d_drm.h"
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#include "fex-drm/virtgpu_drm.h"
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@ -713,6 +714,360 @@ fex_drm_amdgpu_gem_metadata {
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};
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}
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namespace RADEON {
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_gem_create")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_gem_create {
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compat_uint64_t size;
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compat_uint64_t alignment;
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__u32 handle;
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__u32 initial_domain;
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__u32 flags;
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fex_drm_radeon_gem_create() = delete;
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operator drm_radeon_gem_create() const {
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drm_radeon_gem_create val{};
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val.size = size;
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val.alignment = alignment;
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val.handle = handle;
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val.initial_domain = initial_domain;
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val.flags = flags;
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return val;
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}
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fex_drm_radeon_gem_create(struct drm_radeon_gem_create val) {
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size = val.size;
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alignment = val.alignment;
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handle = val.handle;
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initial_domain = val.initial_domain;
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flags = val.flags;
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}
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};
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struct
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FEX_PACKED
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FEX_ANNOTATE("alias-x86_32-drm_radeon_init")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_init_t {
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enum {
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} func;
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compat_ulong_t sarea_priv_offset;
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int32_t is_pci;
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int32_t cp_mode;
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int32_t gart_size;
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int32_t ring_size;
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int32_t usec_timeout;
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uint32_t fb_bpp;
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uint32_t front_offset, front_pitch;
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uint32_t back_offset, back_pitch;
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uint32_t depth_bpp;
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uint32_t depth_offset, depth_pitch;
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compat_ulong_t fb_offset;
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compat_ulong_t mmio_offset;
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compat_ulong_t ring_offset;
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compat_ulong_t ring_rptr_offset;
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compat_ulong_t buffers_offset;
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compat_ulong_t gart_textures_offset;
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fex_drm_radeon_init_t() = delete;
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operator drm_radeon_init_t() const {
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drm_radeon_init_t val{};
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val.sarea_priv_offset = sarea_priv_offset;
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val.is_pci = is_pci;
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val.cp_mode = cp_mode;
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val.gart_size = gart_size;
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val.ring_size = ring_size;
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val.usec_timeout = usec_timeout;
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val.fb_bpp = fb_bpp;
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val.front_offset = front_offset;
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val.front_pitch = front_pitch;
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val.back_offset = back_offset;
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val.back_pitch = back_pitch;
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val.depth_bpp = depth_bpp;
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val.depth_offset = depth_offset;
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val.depth_pitch = depth_pitch;
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val.fb_offset = fb_offset;
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val.mmio_offset = mmio_offset;
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val.ring_offset = ring_offset;
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val.ring_rptr_offset = ring_rptr_offset;
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val.buffers_offset = buffers_offset;
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val.gart_textures_offset = gart_textures_offset;
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return val;
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}
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fex_drm_radeon_init_t(drm_radeon_init_t val) {
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sarea_priv_offset = val.sarea_priv_offset;
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is_pci = val.is_pci;
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cp_mode = val.cp_mode;
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gart_size = val.gart_size;
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ring_size = val.ring_size;
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usec_timeout = val.usec_timeout;
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fb_bpp = val.fb_bpp;
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front_offset = val.front_offset;
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front_pitch = val.front_pitch;
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back_offset = val.back_offset;
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back_pitch = val.back_pitch;
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depth_bpp = val.depth_bpp;
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depth_offset = val.depth_offset;
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depth_pitch = val.depth_pitch;
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fb_offset = val.fb_offset;
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mmio_offset = val.mmio_offset;
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ring_offset = val.ring_offset;
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ring_rptr_offset = val.ring_rptr_offset;
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buffers_offset = val.buffers_offset;
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gart_textures_offset = val.gart_textures_offset;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_clear")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_clear_t {
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uint32_t flags;
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uint32_t clear_color;
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uint32_t clear_depth;
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uint32_t color_mask;
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uint32_t depth_mask;
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compat_ptr<drm_radeon_clear_rect_t> depth_boxes;
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fex_drm_radeon_clear_t() = delete;
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operator drm_radeon_clear_t() const {
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drm_radeon_clear_t val{};
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val.flags = flags;
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val.clear_color = clear_color;
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val.clear_depth = clear_depth;
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val.color_mask = color_mask;
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val.depth_mask = depth_mask;
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val.depth_boxes = depth_boxes;
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return val;
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}
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fex_drm_radeon_clear_t(drm_radeon_clear_t val)
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: depth_boxes {val.depth_boxes} {
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flags = val.flags;
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clear_color = val.clear_color;
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clear_depth = val.clear_depth;
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color_mask = val.color_mask;
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depth_mask = val.depth_mask;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_stipple")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_stipple_t {
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compat_ptr<uint32_t> mask;
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fex_drm_radeon_stipple_t() = delete;
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operator drm_radeon_stipple_t() const {
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drm_radeon_stipple_t val{};
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val.mask = mask;
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return val;
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}
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fex_drm_radeon_stipple_t(drm_radeon_stipple_t val)
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: mask {val.mask} {
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_texture")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_texture_t {
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uint32_t offset;
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int32_t pitch;
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int32_t format;
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int32_t width;
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int32_t height;
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compat_ptr<drm_radeon_tex_image_t> image;
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fex_drm_radeon_texture_t() = delete;
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operator drm_radeon_texture_t() const {
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drm_radeon_texture_t val{};
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val.offset = offset;
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val.pitch = pitch;
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val.format = format;
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val.width = width;
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val.height = height;
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val.image = image;
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return val;
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}
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fex_drm_radeon_texture_t(drm_radeon_texture_t val)
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: image {val.image} {
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offset = val.offset;
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pitch = val.pitch;
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format = val.format;
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width = val.width;
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height = val.height;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_vertex2")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_vertex2_t {
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int32_t idx;
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int32_t discard;
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int32_t nr_states;
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compat_ptr<drm_radeon_state_t> state;
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int32_t nr_prims;
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compat_ptr<drm_radeon_prim_t> prim;
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fex_drm_radeon_vertex2_t() = delete;
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operator drm_radeon_vertex2_t() const {
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drm_radeon_vertex2_t val;
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val.idx = idx;
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val.discard = discard;
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val.nr_states = nr_states;
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val.state = state;
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val.nr_prims = nr_prims;
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val.prim = prim;
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return val;
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}
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fex_drm_radeon_vertex2_t(drm_radeon_vertex2_t val)
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: state {val.state}
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, prim {val.prim} {
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idx = val.idx;
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discard = val.discard;
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nr_states = val.nr_states;
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nr_prims = val.nr_prims;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_cmd_buffer")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_cmd_buffer_t {
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int32_t bufsz;
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compat_ptr<char> buf;
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int32_t nbox;
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compat_ptr<drm_clip_rect> boxes;
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fex_drm_radeon_cmd_buffer_t() = delete;
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operator drm_radeon_cmd_buffer_t() const {
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drm_radeon_cmd_buffer_t val;
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val.bufsz = bufsz;
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val.buf = buf;
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val.nbox = nbox;
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val.boxes = boxes;
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return val;
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}
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fex_drm_radeon_cmd_buffer_t(drm_radeon_cmd_buffer_t val)
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: buf {val.buf}
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, boxes {val.boxes} {
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val.bufsz = bufsz;
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val.nbox = nbox;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_getparam")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_getparam_t {
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int32_t param;
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compat_ptr<void> value;
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fex_drm_radeon_getparam_t() = delete;
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operator drm_radeon_getparam_t() const {
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drm_radeon_getparam_t val;
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val.param = param;
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val.value = value;
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return val;
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}
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fex_drm_radeon_getparam_t(drm_radeon_getparam_t val)
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: value {val.value} {
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val.param = param;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_mem_alloc")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_mem_alloc_t {
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int32_t region;
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int32_t alignment;
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int32_t size;
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compat_ptr<int32_t> region_offset;
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fex_drm_radeon_mem_alloc_t() = delete;
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operator drm_radeon_mem_alloc_t() const {
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drm_radeon_mem_alloc_t val;
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val.region = region;
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val.alignment = alignment;
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val.size = size;
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val.region_offset = region_offset;
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return val;
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}
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fex_drm_radeon_mem_alloc_t(drm_radeon_mem_alloc_t val)
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: region_offset {val.region_offset} {
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val.region = region;
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val.alignment = alignment;
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val.size = size;
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_irq_emit")
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FEX_ANNOTATE("fex-match")
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fex_drm_radeon_irq_emit_t {
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compat_ptr<int32_t> irq_seq;
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fex_drm_radeon_irq_emit_t() = delete;
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operator drm_radeon_irq_emit_t() const {
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drm_radeon_irq_emit_t val;
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val.irq_seq = irq_seq;
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return val;
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}
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fex_drm_radeon_irq_emit_t(drm_radeon_irq_emit_t val)
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: irq_seq {val.irq_seq} {
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}
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};
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struct
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FEX_ANNOTATE("alias-x86_32-drm_radeon_setparam")
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FEX_ANNOTATE("fex-match")
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FEX_PACKED
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fex_drm_radeon_setparam_t {
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uint32_t param;
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compat_int64_t value;
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fex_drm_radeon_setparam_t() = delete;
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operator drm_radeon_setparam_t() const {
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drm_radeon_setparam_t val;
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val.param = param;
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val.value = value;
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return val;
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}
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fex_drm_radeon_setparam_t(drm_radeon_setparam_t val) {
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param = val.param;
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value = val.value;
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}
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};
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}
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namespace MSM {
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struct
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FEX_ANNOTATE("alias-x86_32-drm_msm_timespec")
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@ -1061,6 +1416,7 @@ fex_drm_v3d_submit_csd {
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#include "Tests/LinuxSyscalls/x32/Ioctl/lima_drm.inl"
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#include "Tests/LinuxSyscalls/x32/Ioctl/panfrost_drm.inl"
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#include "Tests/LinuxSyscalls/x32/Ioctl/nouveau_drm.inl"
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#include "Tests/LinuxSyscalls/x32/Ioctl/radeon_drm.inl"
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#include "Tests/LinuxSyscalls/x32/Ioctl/vc4_drm.inl"
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#include "Tests/LinuxSyscalls/x32/Ioctl/v3d_drm.inl"
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44
Source/Tests/LinuxSyscalls/x32/Ioctl/radeon_drm.inl
Normal file
44
Source/Tests/LinuxSyscalls/x32/Ioctl/radeon_drm.inl
Normal file
@ -0,0 +1,44 @@
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_CUSTOM_META(DRM_IOCTL_RADEON_CP_INIT, DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, FEX::HLE::x32::RADEON::fex_drm_radeon_init_t))
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_BASIC_META(DRM_IOCTL_RADEON_CP_START)
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_BASIC_META(DRM_IOCTL_RADEON_CP_STOP)
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_BASIC_META(DRM_IOCTL_RADEON_CP_RESET)
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_BASIC_META(DRM_IOCTL_RADEON_CP_IDLE)
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_BASIC_META(DRM_IOCTL_RADEON_RESET)
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_BASIC_META(DRM_IOCTL_RADEON_FULLSCREEN)
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_BASIC_META(DRM_IOCTL_RADEON_SWAP)
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_CUSTOM_META(DRM_IOCTL_RADEON_CLEAR, DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, FEX::HLE::x32::RADEON::fex_drm_radeon_clear_t))
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_BASIC_META(DRM_IOCTL_RADEON_VERTEX)
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_BASIC_META(DRM_IOCTL_RADEON_INDICES)
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_CUSTOM_META(DRM_IOCTL_RADEON_STIPPLE, DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, FEX::HLE::x32::RADEON::fex_drm_radeon_stipple_t))
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_BASIC_META(DRM_IOCTL_RADEON_INDIRECT)
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_CUSTOM_META(DRM_IOCTL_RADEON_TEXTURE, DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, FEX::HLE::x32::RADEON::fex_drm_radeon_texture_t))
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_CUSTOM_META(DRM_IOCTL_RADEON_VERTEX2, DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, FEX::HLE::x32::RADEON::fex_drm_radeon_vertex2_t))
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_CUSTOM_META(DRM_IOCTL_RADEON_CMDBUF, DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, FEX::HLE::x32::RADEON::fex_drm_radeon_cmd_buffer_t))
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_CUSTOM_META(DRM_IOCTL_RADEON_GETPARAM, DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, FEX::HLE::x32::RADEON::fex_drm_radeon_getparam_t))
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_BASIC_META(DRM_IOCTL_RADEON_FLIP)
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_CUSTOM_META(DRM_IOCTL_RADEON_ALLOC, DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, FEX::HLE::x32::RADEON::fex_drm_radeon_mem_alloc_t))
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_BASIC_META(DRM_IOCTL_RADEON_FREE)
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_BASIC_META(DRM_IOCTL_RADEON_INIT_HEAP)
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_CUSTOM_META(DRM_IOCTL_RADEON_IRQ_EMIT, DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, FEX::HLE::x32::RADEON::fex_drm_radeon_irq_emit_t))
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_BASIC_META(DRM_IOCTL_RADEON_IRQ_WAIT)
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_BASIC_META(DRM_IOCTL_RADEON_CP_RESUME)
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_CUSTOM_META(DRM_IOCTL_RADEON_SETPARAM, DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, FEX::HLE::x32::RADEON::fex_drm_radeon_setparam_t))
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_BASIC_META(DRM_IOCTL_RADEON_SURF_ALLOC)
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_BASIC_META(DRM_IOCTL_RADEON_SURF_FREE)
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_BASIC_META(DRM_IOCTL_RADEON_GEM_INFO)
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_CUSTOM_META(DRM_IOCTL_RADEON_GEM_CREATE, DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, FEX::HLE::x32::RADEON::fex_drm_radeon_gem_create))
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_BASIC_META(DRM_IOCTL_RADEON_GEM_MMAP)
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_BASIC_META(DRM_IOCTL_RADEON_GEM_PREAD)
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_BASIC_META(DRM_IOCTL_RADEON_GEM_PWRITE)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_SET_DOMAIN)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_WAIT_IDLE)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_CS)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_INFO)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_SET_TILING)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_GET_TILING)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_BUSY)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_VA)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_OP)
|
||||
_BASIC_META(DRM_IOCTL_RADEON_GEM_USERPTR)
|
||||
|
||||
@ -178,6 +178,141 @@ namespace FEX::HLE::x32 {
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
uint32_t RADEON_Handler(int fd, uint32_t cmd, uint32_t args) {
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_CP_INIT): {
|
||||
RADEON::fex_drm_radeon_init_t *val = reinterpret_cast<RADEON::fex_drm_radeon_init_t*>(args);
|
||||
drm_radeon_init_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_CP_INIT, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_CLEAR): {
|
||||
RADEON::fex_drm_radeon_clear_t *val = reinterpret_cast<RADEON::fex_drm_radeon_clear_t*>(args);
|
||||
drm_radeon_clear_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_CLEAR, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_STIPPLE): {
|
||||
RADEON::fex_drm_radeon_stipple_t *val = reinterpret_cast<RADEON::fex_drm_radeon_stipple_t*>(args);
|
||||
drm_radeon_stipple_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_STIPPLE, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_TEXTURE): {
|
||||
RADEON::fex_drm_radeon_texture_t *val = reinterpret_cast<RADEON::fex_drm_radeon_texture_t*>(args);
|
||||
drm_radeon_texture_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_TEXTURE, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_VERTEX2): {
|
||||
RADEON::fex_drm_radeon_vertex2_t *val = reinterpret_cast<RADEON::fex_drm_radeon_vertex2_t*>(args);
|
||||
drm_radeon_vertex2_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_VERTEX2, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_CMDBUF): {
|
||||
RADEON::fex_drm_radeon_cmd_buffer_t *val = reinterpret_cast<RADEON::fex_drm_radeon_cmd_buffer_t*>(args);
|
||||
drm_radeon_cmd_buffer_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_CMDBUF, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_GETPARAM): {
|
||||
RADEON::fex_drm_radeon_getparam_t *val = reinterpret_cast<RADEON::fex_drm_radeon_getparam_t*>(args);
|
||||
drm_radeon_getparam_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_GETPARAM, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_ALLOC): {
|
||||
RADEON::fex_drm_radeon_mem_alloc_t *val = reinterpret_cast<RADEON::fex_drm_radeon_mem_alloc_t*>(args);
|
||||
drm_radeon_mem_alloc_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_ALLOC, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_IRQ_EMIT): {
|
||||
RADEON::fex_drm_radeon_irq_emit_t *val = reinterpret_cast<RADEON::fex_drm_radeon_irq_emit_t*>(args);
|
||||
drm_radeon_irq_emit_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_IRQ_EMIT, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_SETPARAM): {
|
||||
RADEON::fex_drm_radeon_setparam_t *val = reinterpret_cast<RADEON::fex_drm_radeon_setparam_t*>(args);
|
||||
drm_radeon_setparam_t Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_SETPARAM, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
case _IOC_NR(FEX_DRM_IOCTL_RADEON_GEM_CREATE): {
|
||||
RADEON::fex_drm_radeon_gem_create *val = reinterpret_cast<RADEON::fex_drm_radeon_gem_create*>(args);
|
||||
drm_radeon_gem_create Host_val = *val;
|
||||
uint64_t Result = ioctl(fd, DRM_IOCTL_RADEON_GEM_CREATE, &Host_val);
|
||||
if (Result != -1) {
|
||||
*val = Host_val;
|
||||
}
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
#define _BASIC_META(x) case _IOC_NR(x):
|
||||
#define _BASIC_META_VAR(x, args...) case _IOC_NR(x):
|
||||
#define _CUSTOM_META(name, ioctl_num)
|
||||
#define _CUSTOM_META_OFFSET(name, ioctl_num, offset)
|
||||
// DRM
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/radeon_drm.inl"
|
||||
{
|
||||
uint64_t Result = ::ioctl(fd, cmd, args);
|
||||
SYSCALL_ERRNO();
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UnhandledIoctl("RADEON", fd, cmd, args);
|
||||
return -EPERM;
|
||||
break;
|
||||
}
|
||||
#undef _BASIC_META
|
||||
#undef _BASIC_META_VAR
|
||||
#undef _CUSTOM_META
|
||||
#undef _CUSTOM_META_OFFSET
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
uint32_t MSM_Handler(int fd, uint32_t cmd, uint32_t args) {
|
||||
switch (_IOC_NR(cmd)) {
|
||||
case _IOC_NR(FEX_DRM_IOCTL_MSM_WAIT_FENCE): {
|
||||
@ -435,6 +570,9 @@ namespace FEX::HLE::x32 {
|
||||
if (strcmp(Version.name, "amdgpu") == 0) {
|
||||
FDToHandler.SetFDHandler(fd, AMDGPU_Handler);
|
||||
}
|
||||
else if (strcmp(Version.name, "radeon") == 0) {
|
||||
FDToHandler.SetFDHandler(fd, RADEON_Handler);
|
||||
}
|
||||
else if (strcmp(Version.name, "msm") == 0) {
|
||||
FDToHandler.SetFDHandler(fd, MSM_Handler);
|
||||
}
|
||||
@ -611,6 +749,7 @@ namespace FEX::HLE::x32 {
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/lima_drm.inl"
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/panfrost_drm.inl"
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/nouveau_drm.inl"
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/radeon_drm.inl"
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/vc4_drm.inl"
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/v3d_drm.inl"
|
||||
#include "Tests/LinuxSyscalls/x32/Ioctl/virtio_drm.inl"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user