diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json
index d505cc09d..34eb6d7ad 100644
--- a/unittests/InstructionCountCI/FlagM/H0F38.json
+++ b/unittests/InstructionCountCI/FlagM/H0F38.json
@@ -33,89 +33,55 @@
       ]
     },
     "adcx eax, ebx": {
-      "ExpectedInstructionCount": 15,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "0x66 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, lo",
-        "mov w21, w6",
-        "mov w22, w4",
-        "add w23, w21, w20",
-        "add w4, w22, w23",
-        "mrs x22, nzcv",
-        "cmp w4, w21",
-        "cset x23, lo",
-        "cmp w4, w21",
-        "cset x21, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x21, x23, eq",
-        "eor x20, x20, #0x1",
-        "msr nzcv, x22",
-        "rmif x20, #63, #nzCv"
+        "mrs x20, nzcv",
+        "cfinv",
+        "adcs w4, w6, w4",
+        "rmif x20, #28, #NZcV",
+        "cfinv"
       ]
     },
     "adcx rax, rbx": {
-      "ExpectedInstructionCount": 13,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "0x66 REX.W 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, lo",
-        "add x21, x6, x20",
-        "add x4, x4, x21",
-        "mrs x21, nzcv",
-        "cmp x4, x6",
-        "cset x22, lo",
-        "cmp x4, x6",
-        "cset x23, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x23, x22, eq",
-        "eor x20, x20, #0x1",
-        "msr nzcv, x21",
-        "rmif x20, #63, #nzCv"
+        "mrs x20, nzcv",
+        "cfinv",
+        "adcs x4, x6, x4",
+        "rmif x20, #28, #NZcV",
+        "cfinv"
       ]
     },
     "adox eax, ebx": {
-      "ExpectedInstructionCount": 14,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "0xf3 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, vs",
-        "mov w21, w6",
-        "mov w22, w4",
-        "add w23, w21, w20",
-        "add w4, w22, w23",
-        "mrs x22, nzcv",
-        "cmp w4, w21",
-        "cset x23, lo",
-        "cmp w4, w21",
-        "cset x21, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x21, x23, eq",
-        "msr nzcv, x22",
-        "rmif x20, #0, #nzcV"
+        "mrs x20, nzcv",
+        "ccmp wzr, #0, #nzcv, vs",
+        "adcs w4, w6, w4",
+        "ccmp wzr, #0, #nzcV, lo",
+        "rmif x20, #28, #NZCv"
       ]
     },
     "adox rax, rbx": {
-      "ExpectedInstructionCount": 12,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "0xf3 REX.W 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, vs",
-        "add x21, x6, x20",
-        "add x4, x4, x21",
-        "mrs x21, nzcv",
-        "cmp x4, x6",
-        "cset x22, lo",
-        "cmp x4, x6",
-        "cset x23, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x23, x22, eq",
-        "msr nzcv, x21",
-        "rmif x20, #0, #nzcV"
+        "mrs x20, nzcv",
+        "ccmp wzr, #0, #nzcv, vs",
+        "adcs x4, x6, x4",
+        "ccmp wzr, #0, #nzcV, lo",
+        "rmif x20, #28, #NZCv"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json
index 33f818a04..205fe0dd1 100644
--- a/unittests/InstructionCountCI/FlagM/Primary.json
+++ b/unittests/InstructionCountCI/FlagM/Primary.json
@@ -2167,21 +2167,19 @@
       ]
     },
     "test al, 1": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": "0xa8",
       "ExpectedArm64ASM": [
         "and w26, w4, #0x1",
-        "cmn wzr, w26, lsl #24",
-        "cfinv"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "test ax, 1": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
         "and w26, w4, #0x1",
-        "cmn wzr, w26, lsl #16",
-        "cfinv"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "test eax, 1": {
diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
index 7d1d1eeb7..cb21516e9 100644
--- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -2125,12 +2125,11 @@
       ]
     },
     "test bl, 1": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": "GROUP2 0xf6 /0",
       "ExpectedArm64ASM": [
         "and w26, w6, #0x1",
-        "cmn wzr, w26, lsl #24",
-        "cfinv"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "not bl": {
@@ -2212,12 +2211,11 @@
       ]
     },
     "test bx, 1": {
-      "ExpectedInstructionCount": 3,
+      "ExpectedInstructionCount": 2,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
         "and w26, w6, #0x1",
-        "cmn wzr, w26, lsl #16",
-        "cfinv"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "test ebx, 1": {
diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json
index 1f34fb8e8..344e48881 100644
--- a/unittests/InstructionCountCI/FlagM/x87.json
+++ b/unittests/InstructionCountCI/FlagM/x87.json
@@ -6434,7 +6434,7 @@
       ]
     },
     "fcmovu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xda 11b 0xd8 /1"
       ],
@@ -6442,9 +6442,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -6453,12 +6451,11 @@
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xd9 /1"
       ],
@@ -6466,25 +6463,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xda /1"
       ],
@@ -6492,25 +6486,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdb /1"
       ],
@@ -6518,25 +6509,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdc /1"
       ],
@@ -6544,25 +6532,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdd /1"
       ],
@@ -6570,25 +6555,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xde /1"
       ],
@@ -6596,25 +6578,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdf /1"
       ],
@@ -6622,21 +6601,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fucompp": {
@@ -7396,7 +7372,7 @@
       ]
     },
     "fcmovnu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xdb 11b 0xd8 /3"
       ],
@@ -7404,9 +7380,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -7415,12 +7389,11 @@
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xd9 /3"
       ],
@@ -7428,25 +7401,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xda /3"
       ],
@@ -7454,25 +7424,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdb /3"
       ],
@@ -7480,25 +7447,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdc /3"
       ],
@@ -7506,25 +7470,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdd /3"
       ],
@@ -7532,25 +7493,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xde /3"
       ],
@@ -7558,25 +7516,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdf /3"
       ],
@@ -7584,21 +7539,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fnclex": {
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json
index 43d6f410d..1061aa664 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64.json
@@ -3785,7 +3785,7 @@
       ]
     },
     "fcmovu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xda 11b 0xd8 /1"
       ],
@@ -3793,9 +3793,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -3804,12 +3802,11 @@
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xd9 /1"
       ],
@@ -3817,25 +3814,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xda /1"
       ],
@@ -3843,25 +3837,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdb /1"
       ],
@@ -3869,25 +3860,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdc /1"
       ],
@@ -3895,25 +3883,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdd /1"
       ],
@@ -3921,25 +3906,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xde /1"
       ],
@@ -3947,25 +3929,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdf /1"
       ],
@@ -3973,21 +3952,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fucompp": {
@@ -4677,7 +4653,7 @@
       ]
     },
     "fcmovnu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xdb 11b 0xd8 /3"
       ],
@@ -4685,9 +4661,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -4696,12 +4670,11 @@
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xd9 /3"
       ],
@@ -4709,25 +4682,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xda /3"
       ],
@@ -4735,25 +4705,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdb /3"
       ],
@@ -4761,25 +4728,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdc /3"
       ],
@@ -4787,25 +4751,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdd /3"
       ],
@@ -4813,25 +4774,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xde /3"
       ],
@@ -4839,25 +4797,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdf /3"
       ],
@@ -4865,21 +4820,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fnclex": {
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index 86304e1e5..8690369d8 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -858,89 +858,61 @@
       ]
     },
     "adcx eax, ebx": {
-      "ExpectedInstructionCount": 15,
+      "ExpectedInstructionCount": 7,
       "Comment": [
         "0x66 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, lo",
-        "mov w21, w6",
-        "mov w22, w4",
-        "add w23, w21, w20",
-        "add w4, w22, w23",
-        "mrs x22, nzcv",
-        "cmp w4, w21",
-        "cset x23, lo",
-        "cmp w4, w21",
-        "cset x21, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x21, x23, eq",
-        "eor x20, x20, #0x1",
-        "bfi w22, w20, #29, #1",
-        "msr nzcv, x22"
+        "mrs x20, nzcv",
+        "eor w21, w20, #0x20000000",
+        "msr nzcv, x21",
+        "adcs w4, w6, w4",
+        "cset w21, lo",
+        "bfi w20, w21, #29, #1",
+        "msr nzcv, x20"
       ]
     },
     "adcx rax, rbx": {
-      "ExpectedInstructionCount": 13,
+      "ExpectedInstructionCount": 7,
       "Comment": [
         "0x66 REX.W 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, lo",
-        "add x21, x6, x20",
-        "add x4, x4, x21",
-        "mrs x21, nzcv",
-        "cmp x4, x6",
-        "cset x22, lo",
-        "cmp x4, x6",
-        "cset x23, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x23, x22, eq",
-        "eor x20, x20, #0x1",
-        "bfi w21, w20, #29, #1",
-        "msr nzcv, x21"
+        "mrs x20, nzcv",
+        "eor w21, w20, #0x20000000",
+        "msr nzcv, x21",
+        "adcs x4, x6, x4",
+        "cset w21, lo",
+        "bfi w20, w21, #29, #1",
+        "msr nzcv, x20"
       ]
     },
     "adox eax, ebx": {
-      "ExpectedInstructionCount": 14,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "0xf3 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, vs",
-        "mov w21, w6",
-        "mov w22, w4",
-        "add w23, w21, w20",
-        "add w4, w22, w23",
-        "mrs x22, nzcv",
-        "cmp w4, w21",
-        "cset x23, lo",
-        "cmp w4, w21",
-        "cset x21, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x21, x23, eq",
-        "bfi w22, w20, #28, #1",
-        "msr nzcv, x22"
+        "mrs x20, nzcv",
+        "ccmp wzr, #0, #nzcv, vs",
+        "adcs w4, w6, w4",
+        "cset w21, hs",
+        "bfi w20, w21, #28, #1",
+        "msr nzcv, x20"
       ]
     },
     "adox rax, rbx": {
-      "ExpectedInstructionCount": 12,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "0xf3 REX.W 0x0f 0x38 0xf6"
       ],
       "ExpectedArm64ASM": [
-        "cset w20, vs",
-        "add x21, x6, x20",
-        "add x4, x4, x21",
-        "mrs x21, nzcv",
-        "cmp x4, x6",
-        "cset x22, lo",
-        "cmp x4, x6",
-        "cset x23, ls",
-        "cmp x20, #0x1 (1)",
-        "csel x20, x23, x22, eq",
-        "bfi w21, w20, #28, #1",
-        "msr nzcv, x21"
+        "mrs x20, nzcv",
+        "ccmp wzr, #0, #nzcv, vs",
+        "adcs x4, x6, x4",
+        "cset w21, hs",
+        "bfi w20, w21, #28, #1",
+        "msr nzcv, x20"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json
index 00bc905ab..367d7d6cf 100644
--- a/unittests/InstructionCountCI/Primary.json
+++ b/unittests/InstructionCountCI/Primary.json
@@ -3537,25 +3537,19 @@
       ]
     },
     "test al, 1": {
-      "ExpectedInstructionCount": 5,
+      "ExpectedInstructionCount": 2,
       "Comment": "0xa8",
       "ExpectedArm64ASM": [
         "and w26, w4, #0x1",
-        "cmn wzr, w26, lsl #24",
-        "mrs x20, nzcv",
-        "eor w20, w20, #0x20000000",
-        "msr nzcv, x20"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "test ax, 1": {
-      "ExpectedInstructionCount": 5,
+      "ExpectedInstructionCount": 2,
       "Comment": "0xa9",
       "ExpectedArm64ASM": [
         "and w26, w4, #0x1",
-        "cmn wzr, w26, lsl #16",
-        "mrs x20, nzcv",
-        "eor w20, w20, #0x20000000",
-        "msr nzcv, x20"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "test eax, 1": {
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index ae6f3b8fe..38ac2eff8 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -2506,14 +2506,11 @@
       ]
     },
     "test bl, 1": {
-      "ExpectedInstructionCount": 5,
+      "ExpectedInstructionCount": 2,
       "Comment": "GROUP2 0xf6 /0",
       "ExpectedArm64ASM": [
         "and w26, w6, #0x1",
-        "cmn wzr, w26, lsl #24",
-        "mrs x20, nzcv",
-        "eor w20, w20, #0x20000000",
-        "msr nzcv, x20"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "not bl": {
@@ -2602,14 +2599,11 @@
       ]
     },
     "test bx, 1": {
-      "ExpectedInstructionCount": 5,
+      "ExpectedInstructionCount": 2,
       "Comment": "GROUP2 0xf7 /0",
       "ExpectedArm64ASM": [
         "and w26, w6, #0x1",
-        "cmn wzr, w26, lsl #16",
-        "mrs x20, nzcv",
-        "eor w20, w20, #0x20000000",
-        "msr nzcv, x20"
+        "cmp w26, #0x0 (0)"
       ]
     },
     "test ebx, 1": {
diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json
index 15d3fd314..837fd17a8 100644
--- a/unittests/InstructionCountCI/x87.json
+++ b/unittests/InstructionCountCI/x87.json
@@ -6433,7 +6433,7 @@
       ]
     },
     "fcmovu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xda 11b 0xd8 /1"
       ],
@@ -6441,9 +6441,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -6452,12 +6450,11 @@
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xd9 /1"
       ],
@@ -6465,25 +6462,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xda /1"
       ],
@@ -6491,25 +6485,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdb /1"
       ],
@@ -6517,25 +6508,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdc /1"
       ],
@@ -6543,25 +6531,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdd /1"
       ],
@@ -6569,25 +6554,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xde /1"
       ],
@@ -6595,25 +6577,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdf /1"
       ],
@@ -6621,21 +6600,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fucompp": {
@@ -7395,7 +7371,7 @@
       ]
     },
     "fcmovnu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xdb 11b 0xd8 /3"
       ],
@@ -7403,9 +7379,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -7414,12 +7388,11 @@
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xd9 /3"
       ],
@@ -7427,25 +7400,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xda /3"
       ],
@@ -7453,25 +7423,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdb /3"
       ],
@@ -7479,25 +7446,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdc /3"
       ],
@@ -7505,25 +7469,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdd /3"
       ],
@@ -7531,25 +7492,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xde /3"
       ],
@@ -7557,25 +7515,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdf /3"
       ],
@@ -7583,21 +7538,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr q3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr q4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str q2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str q2, [x0, #1040]"
       ]
     },
     "fnclex": {
diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json
index 1329af540..0cde9a046 100644
--- a/unittests/InstructionCountCI/x87_f64.json
+++ b/unittests/InstructionCountCI/x87_f64.json
@@ -3805,7 +3805,7 @@
       ]
     },
     "fcmovu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xda 11b 0xd8 /1"
       ],
@@ -3813,9 +3813,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -3824,12 +3822,11 @@
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xd9 /1"
       ],
@@ -3837,25 +3834,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xda /1"
       ],
@@ -3863,25 +3857,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdb /1"
       ],
@@ -3889,25 +3880,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdc /1"
       ],
@@ -3915,25 +3903,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdd /1"
       ],
@@ -3941,25 +3926,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xde /1"
       ],
@@ -3967,25 +3949,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xda 11b 0xdf /1"
       ],
@@ -3993,21 +3972,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eon w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fucompp": {
@@ -4698,7 +4674,7 @@
       ]
     },
     "fcmovnu st0, st0": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 13,
       "Comment": [
         "0xdb 11b 0xd8 /3"
       ],
@@ -4706,9 +4682,7 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
@@ -4717,12 +4691,11 @@
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st1": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xd9 /3"
       ],
@@ -4730,25 +4703,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x1 (1)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x1 (1)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st2": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xda /3"
       ],
@@ -4756,25 +4726,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x2 (2)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x2 (2)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st3": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdb /3"
       ],
@@ -4782,25 +4749,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x3 (3)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x3 (3)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st4": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdc /3"
       ],
@@ -4808,25 +4772,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x4 (4)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x4 (4)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st5": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdd /3"
       ],
@@ -4834,25 +4795,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x5 (5)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x5 (5)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st6": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xde /3"
       ],
@@ -4860,25 +4818,22 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x6 (6)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x6 (6)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fcmovnu st0, st7": {
-      "ExpectedInstructionCount": 18,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0xdb 11b 0xdf /3"
       ],
@@ -4886,21 +4841,18 @@
         "eor w20, w26, w26, lsr #4",
         "eor w20, w20, w20, lsr #2",
         "eor w20, w20, w20, lsr #1",
-        "mrs x21, nzcv",
-        "tst w20, #0x1",
-        "csetm x20, ne",
+        "sbfx x20, x20, #0, #1",
         "dup v2.2d, x20",
         "ldrb w20, [x28, #1019]",
-        "add w22, w20, #0x7 (7)",
-        "and w22, w22, #0x7",
-        "add x0, x28, x22, lsl #4",
+        "add w21, w20, #0x7 (7)",
+        "and w21, w21, #0x7",
+        "add x0, x28, x21, lsl #4",
         "ldr d3, [x0, #1040]",
         "add x0, x28, x20, lsl #4",
         "ldr d4, [x0, #1040]",
         "bsl v2.16b, v3.16b, v4.16b",
         "add x0, x28, x20, lsl #4",
-        "str d2, [x0, #1040]",
-        "msr nzcv, x21"
+        "str d2, [x0, #1040]"
       ]
     },
     "fnclex": {