Ryan Houdek
bfad5d6925
Ensure serialize isn't covering too much of the instruction space
...
Makes sure to jump to the second indirect table so it doesn't cover the
whole row. This time with unittests to ensure it is correct.
Supercedes #6113 .
2026-11-09 12:42:46 -08:00
Ryan Houdek
36aec0d54d
DiskCache: Moves SVE/AVX from HostFeatureHash to ProcessHash
...
Annoyingly these are technically host features but they end up being
process feature hash bits because they change between Linux, wow64, and
arm64ec.
This now makes the HostFeaturesHash match between the three which is
what we want. While the process feature bits change between them.
Adds an info log to the DiskCache startup for confirmation.
2026-11-05 13:45:13 -08:00
Ryan Houdek
61523a6db1
OpcodeDispatcher: Make sure xsetbv works correctly
...
I had missed testing this instruction because it doesn't show up in the
regular instruction tables that I was checking for system instructions.
2026-11-04 14:42:03 -08:00
Justin Becker
e873aadf2e
NIT: Style
2026-11-02 14:41:33 -08:00
Justin Becker
e7a1904200
OpcodeDispatcher: Add SHA256RNDS2 peephole
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Testing on X2E suggests a roughly 2x performance gain using this new translation
2026-11-02 14:41:33 -08:00
Ryan Houdek
13c30c2b60
OpcodeDispatcher: Fixes AVX-NE-Convert
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Now that this was hardware tested, it found that I accidentally copy and
pasted the BF16 implementation on to FP16 instructions.
2026-10-27 17:59:19 -07:00
Ryan Houdek
983aa475c1
OpcodeDispatcher/x87: Implement support for FIP
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Only enabled with `FEX_JITFEATURES=enablex87fip`. This way most games
don't pay the cost.
For #6054
2026-10-24 19:18:22 -07:00
Ryan Houdek
648f883265
OpcodeDispatcher: Implement x87 FIP for save/restore operations
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Not fully implemented, but gets the basic saving and restoring in place.
2026-10-23 16:38:33 -07:00
Ryan Houdek
8e6060827e
OpcodeDispatcher: Fixes swapgs on 32-bit
...
It was returning the incorrect implementation on 32-bit. Copies the
system instruction test to 32-bit with proper fixups for 32-bit support
as well. Technically this changes codegen but wasn't seen in practice so
save a number bump.
2026-10-22 16:06:17 -07:00
Ryan Houdek
465395dede
OpcodeDispatcher: Implement SLDT
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Not 100% correct because the Linux kernel has some cheeky false data
return value when an LDT gets installed. But FEX can't really do it
properly today so whatever.
2026-10-22 15:29:16 -07:00
Ryan Houdek
fd4c097628
AVX256: Implement AVX_NE_CONVERT
...
Doesn't require SVE_BF16, only BF16 because we split the operation even
on 256-bit.
2026-10-20 17:29:04 -07:00
Ryan Houdek
36d3bb6185
AVX128: Implement AVX_NE_CONVERT
2026-10-20 17:17:48 -07:00
Ryan Houdek
f256d97ddb
FEXCore: Wire up support for SERIALIZE
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Trivial instruction.
2026-10-19 14:11:06 -07:00
Justin Becker
5ec147109e
Implement peephole optimization for vpcmpeqd + vgatherdps
...
This peephole removes unnecessary masking operations when the mask is
provably all 1s. This improves performance in GB7 'Asset Compression' by
about 2% with SVE and about 4% without SVE.
2026-10-05 15:17:58 -07:00
Justin Becker
079a69dde2
Style nits
2026-09-30 15:22:22 -07:00
Justin Becker
6788bcf264
x87: complete FXAM implementation
2026-09-30 15:07:32 -07:00
Justin Becker
af8770005b
Clang format
2026-09-22 12:53:05 -07:00
Justin Becker
e2f0cf41d8
More cleanup
2026-09-22 12:53:05 -07:00
Justin Becker
638329278c
Inlined PCMPXSTRX
...
Improves performance for SSE4.2 String operations by ~10x by emitting inline ASM instead of jumping to a C++ helper.
Performance numbers from a simple microbenchmark vs the existing C++ implementation:
| | Equal Any | Ranges | Equal Each | Equal Ordered |
|---------------|-----------|--------|------------|---------------|
| **pcmpestri** | 13.40× | 9.71× | 19.38× | 14.07× |
| **pcmpestrm** | 13.12× | 9.54× | 18.73× | 13.80× |
| **pcmpistri** | 11.75× | 9.19× | 17.63× | 12.80× |
| **pcmpistrm** | 11.39× | 8.83× | 16.31× | 12.26× |
2026-09-22 12:50:02 -07:00
Simon Scherer
93def42061
OpcodeDispatcher: Fix RestoreX87State to rotate MM regs by Top of Stack
2026-09-15 16:38:36 -07:00
Ryan Houdek
1523142540
OpcodeDispatcher: Removes DST_RAX from CMP/TEST
2026-09-15 15:00:03 -07:00
Ryan Houdek
5743282944
OpcodeDispatcher: Removes DST_RAX from SBB
2026-09-15 15:00:02 -07:00
Ryan Houdek
9d936a8989
OpcodeDispatcher: Removes DST_RAX from ADC
2026-09-15 15:00:02 -07:00
Ryan Houdek
1e95181b34
OpcodeDispatcher: Removes DST_RAX from ALUOp operations.
2026-09-15 15:00:01 -07:00
Ryan Houdek
e8084e3f11
OpcodeDispatcher: Remove DST_RAX from FNSTSW
2026-09-15 15:00:00 -07:00
Ryan Houdek
ea263166c5
OpcodeDispatcher: Removes SRC_RCX from shift/rotate ops
...
These are all similar to each other with similar code. Hit them at the
same time.
2026-09-15 11:56:09 -07:00
Ryan Houdek
58e0e1a03a
OpcodeDispatcher: Removes SRC_RAX from XCHG
2026-09-14 16:03:31 -07:00
Justin Becker
89a13cd5fd
AVX-VNNI
2026-09-10 15:56:03 -07:00
Ryan Houdek
38c9f14dbd
OpcodeDispatcher: Explicitly handle no-nop vector moves
...
Just be very explicit about this rather than questioning why MMX moves
can't be a nop in the regular vector move code.
Doesn't change codegen so binarycacheversion doesn't need to change.
2026-09-04 12:19:21 -07:00
Simon Scherer
8ed4c52d58
OpcodeDispatcher: Don't skip the MMX state transition for same-register writes in MOVVectorUnalignedOp
2026-09-04 17:00:45 +02:00
Simon Scherer
7236c2bf0a
Fix x87 tag word not updating on FST ST(0) self-store
2026-09-04 11:51:12 +02:00
Simon Scherer
d1b2333195
OpcodeDispatcher: Clear C1 to 0 for X87ModifySTP (fdecstp and fincstp)
2026-09-04 07:22:05 +02:00
jubecker
61d94ac117
Potential improvement for *PMULHRSW
2026-09-02 14:31:18 -07:00
Simon Scherer
4a7fda4516
OpcodeDispatcher: Preserve IE exception flag for FCOMI and FTST
2026-09-02 07:42:04 +02:00
LC
62c9c130c4
Merge pull request #5864 from simon902/pf2id_saturation
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Fix pf2id overflow saturation
2026-08-27 09:16:04 -04:00
Simon Scherer
b21a8dafa7
OpcodeDispatcher: Fix pf2id overflow saturation
2026-08-27 11:50:45 +02:00
Simon Scherer
5ab2c723ff
OpcodeDispatcher: For PF2IWOp use VSQXTN instead of VUnZip to saturate values falling outside the 16-bit range
2026-08-27 09:36:17 +02:00
Ryan Houdek
6646a5cc72
OpcodeDispatcher: Fixes SHLD by 16 behaviour
...
We were assuming that SHLD undefined behaviour matches SHL, but the
specification actually changes a `ge` comparison to `gt`, which means a
shift of 16 isn't UB!
Thanks to the impeccable @OFFTKP in #5842 for bringing this up as it took a bit
for me to figure out what was actually wrong here. I modified their
unittest to cover more just to ensure we don't break it.
2026-08-25 15:15:36 -07:00
Simon Scherer
7f0bdf8d63
OpcodeDispatcher: Zero OF, SF and AF for FCOMI and FCOMIF64
2026-08-06 16:29:29 +02:00
Ryan Houdek
c4a5ac892f
AVX128: Optimize 256-bit vmovmaskpd as well
...
Similar to #5757 , but once the elements have been zipped together, we
can treat it identically to the 128-bit 32-bit element path.
Closes #3782
2026-07-17 13:15:47 -07:00
moonfloww
3680282b30
new vmovmsk from 11 to 7 ins.
2026-07-16 13:57:12 +02:00
LC
2934b01d58
Vector: Indicate 128-bit zero vector in DefaultX87State()
...
Same functional behavior, just makes it visually match the store size
below. Technically also avoids delegating off to the 64-bit element
path if a 128-bit constant zero is already loaded.
2026-07-13 14:07:12 -04:00
LC
fb2cdc8541
Crypto: Clarify zero vector size in SHA1RNDS4Op()
...
This ends up zeroing out the whole 128-bit vector.
2026-07-12 18:49:27 -04:00
LC
9d3c388664
Crypto: Make use of XAR in SHA1NEXTE when available
...
Lets us shave an instruction off on hardware that supports XAR.
Closes #5730
2026-07-12 16:02:12 -04:00
LC
c7f52bcee4
Vector: Centralize masking in InsertScalarFCMPOp
...
Ensures that even if someone threw bogus constants in the upper bits of
the immediate, that the special-cased comparison types would still be
handled properly.
We can move the masking in the AVX variant too, just to be consistent.
2026-07-11 16:07:19 -04:00
Ryan Houdek
37814111de
Merge pull request #5692 from lioncash/unary
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Vector: Use unary handler for scalar unary insertions
2026-07-10 10:26:44 -07:00
LC
401e542fcd
Vector: Use unary handler for scalar unary insertions
...
Same behavior, but just uses a more proper handler.
2026-07-10 07:27:54 -04:00
LC
210514f74b
Vector: LoadSourceGPR -> LoadSourceFPR for MASKMOVOp
2026-07-10 07:24:39 -04:00
Ryan Houdek
3370d9af15
Merge pull request #5670 from simon902/MOVDoverride
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Fix movd when prefixed with 0x66
2026-07-09 13:02:08 -07:00
Ryan Houdek
9306de79ad
Merge pull request #5667 from simon902/CVTTSS2SIOverride
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Fix cvttss2si when prefixed with 0x66
2026-07-09 12:52:00 -07:00
Ryan Houdek