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Author SHA1 Message Date
Alyssa Rosenzweig
582c3dae6e OpcodeDispatcher: use LoadConstantShift for SHLD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
2abac03ab0 OpcodeDispatcher: add LoadConstantShift helper 
shows up a bunch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
8cc684fa12 OpcodeDispatcher: drop misinformed comment 
tbnz only tests a single bit, not a mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
d92de1d947 OpcodeDispatcher: drop result masking for shifts 
flag calcs are fine with upper garbage.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
202a60b77a
Merge pull request #3549 from alyssarosenzweig/constprop/dce 
ConstProp: drop dead code
 2024-04-03 11:22:30 -04:00
Alyssa Rosenzweig
aa8d04c341
Merge pull request #3551 from alyssarosenzweig/opt/negate-adds 
Negate more to inline constants
 2024-04-03 11:22:01 -04:00
Alyssa Rosenzweig
d6425d05f3 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:57:06 -04:00
Alyssa Rosenzweig
e07c81a5e7 ConstProp: also negate sub -> add 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:56:59 -04:00
Alyssa Rosenzweig
fa76961873 ConstProp: negate adds -> subs 
the arm ops are equiv, even though the x86 isn't (due to inverted carry).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:53:21 -04:00
Alyssa Rosenzweig
b92c206db9 ConstProp: rm your deadcode 
not sure who this is supposed to be helping.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:21:48 -04:00
Alyssa Rosenzweig
efff942724 ConstProp: drop my deadcode 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:21:48 -04:00
Alyssa Rosenzweig
8d32113521 ConstProp: rm relic of x86 jit 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:21:48 -04:00
Alyssa Rosenzweig
37f2b417e4
Merge pull request #3546 from alyssarosenzweig/flag/cleanup 
Minor cleanups around flags
 2024-04-02 11:29:19 -04:00
Alyssa Rosenzweig
bd0b5eceb8
Merge pull request #3545 from alyssarosenzweig/opt/pf-scalar 
Use scalar integer code to calculate PF
 2024-04-02 11:28:53 -04:00
Alyssa Rosenzweig
b632f7215c
Merge pull request #3544 from alyssarosenzweig/ra/zero-multiple 
OpcodeDispatcher: drop ZeroMultipleFlags
 2024-04-02 11:27:45 -04:00
Ryan Houdek
e8abc88702
Merge pull request #3542 from alyssarosenzweig/ra/rep 
Eliminate xblock liveness with rep cmp/lod/scas
 2024-04-02 04:24:24 -07:00
Ryan Houdek
29c6281e11
Merge pull request #3539 from alyssarosenzweig/ra/rol-ror2 
rewrite ROL/ROR
 2024-04-02 00:17:08 -07:00
Ryan Houdek
4214d9bda0
Merge pull request #3538 from pmatos/OffsetofOoB 
Fix reference to out of bounds address in offsetof
 2024-04-01 19:41:57 -07:00
Alyssa Rosenzweig
0a7b3efb41 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:50 -04:00
Alyssa Rosenzweig
067a5444dc OpcodeDispatcher: use HandleNZ00Write 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:38 -04:00
Alyssa Rosenzweig
c7f159972d OpcodeDispatcher: rm pointless NZCV loads 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:38 -04:00
Alyssa Rosenzweig
a70d0a5dd4 OpcodeDispatcher: rm unnecessary NZCV dirtying 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 16:42:38 -04:00
Ryan Houdek
cd9ffd2045
Merge pull request #3536 from alyssarosenzweig/ra/rcl-rcr 
OpcodeDispatcher: eliminate xblock liveness for rcl/rcr
 2024-04-01 11:44:37 -07:00
Alyssa Rosenzweig
5c590b9a50 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:13:09 -04:00
Alyssa Rosenzweig
eb4bb5875e OpcodeDispatcher: absorb invert into PF calculation 
with xorn

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:12:33 -04:00
Alyssa Rosenzweig
3b052e826f OpcodeDispatcher: calculate PF with integer ops 
based on clang's __builtin_parity

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:12:32 -04:00
Alyssa Rosenzweig
65ec191dc1 IR: add XornShift 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 14:12:32 -04:00
Alyssa Rosenzweig
b1ddd8cd3b
Merge pull request #3541 from alyssarosenzweig/opt/clc 
optimize clc
 2024-04-01 13:51:10 -04:00
Alyssa Rosenzweig
f2d001e721
Merge pull request #3543 from alyssarosenzweig/ra/dead-code 
RA: drop dead block interference code
 2024-04-01 13:51:00 -04:00
Alyssa Rosenzweig
7852909cc4 OpcodeDispatcher: simplify IsNZCV 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 13:50:00 -04:00
Alyssa Rosenzweig
fad243d3f6 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 13:48:27 -04:00
Alyssa Rosenzweig
f8b68d8b5a OpcodeDispatcher: drop ZeroMultipleFlags 
lot of complexity for only a single interesting case. we can massively simplify.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-01 13:48:11 -04:00
Ryan Houdek
e2a095372e
Merge pull request #3534 from Sonicadvance1/move_ir_defines 
FEXCore: Move nearly all IR definitions to internal
 2024-04-01 10:00:20 -07:00
Ryan Houdek
5c29c9d464
Merge pull request #3527 from Sonicadvance1/move_type_defines 
Moves FHU TypeDefines to FEXCore includes
 2024-04-01 08:57:22 -07:00
Ryan Houdek
3bed305660
Merge pull request #3526 from Sonicadvance1/move_codeloader 
FEXCore: Moves CodeLoader to frontend
 2024-04-01 07:52:02 -07:00
Ryan Houdek
f6639c3594
Merge pull request #3525 from Sonicadvance1/move_cpubackend 
FEXCore: Moves CPUBackend definition internal
 2024-04-01 06:47:34 -07:00
Paulo Matos
96087a69fa Fix reference to OoB address in offsetof and remove rflags printout 
Adjust static array size to match new size.
Remove rflags from printing code and adjust offsets - fixes
printing off-by-one error.
 2024-04-01 13:13:17 +02:00
Alyssa Rosenzweig
ca1ec232c9 RA: drop dead block interference code 
Unused, and new RA won't use it either. Torch it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:51:11 -04:00
Alyssa Rosenzweig
ad0dd34412 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:31:38 -04:00
Alyssa Rosenzweig
7b1bb159fa OpcodeDispatcher: use ForeachDirection for scas 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:31:38 -04:00
Alyssa Rosenzweig
5c7f2934de OpcodeDispatcher: use ForeachDirection for lods 
eliminates xblock live

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:29:29 -04:00
Alyssa Rosenzweig
5d79d4eb50 OpcodeDispatcher: use ForeachDirection for CMPS 
eliminates xblock liveness

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:29:16 -04:00
Alyssa Rosenzweig
3f66173bc7 OpcodeDispatcher: add ForeachDirection helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:28:56 -04:00
Alyssa Rosenzweig
b64a594b16 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:01:44 -04:00
Alyssa Rosenzweig
4452f0acba ConstProp: optimize rmif with 0 for clc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 20:01:44 -04:00
Alyssa Rosenzweig
784cdd7b6b InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 19:54:14 -04:00
Alyssa Rosenzweig
1a1545da0f OpcodeDispatcher: rework rep cmp 
1. pull flag calculation out of the loop body for perf
2. fully rotate the inner loop to save an instruction per iteration
3. hoist the rcx=0 jump to avoid computing df when rcx=0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 19:54:00 -04:00
Alyssa Rosenzweig
a70ea30c02 IR: add CondSubNZCV (ccmp) instruction 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 17:50:57 -04:00
Alyssa Rosenzweig
2aa1fd7fa3 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 14:47:19 -04:00
Alyssa Rosenzweig
15b86e4c5a OpcodeDispatcher: rewrite ROL/ROR 
single unified implementation for ROL & ROR (instead of 4 cases). no more
deferred flags because it's easy to shoot ourselves in the foot with deferred
flags w.r.t the new RA design, and rotates are rare enough with very efficient
flag calculations such that the extra JIT overhead should be minimal to DCE the
resulting calculations later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-03-31 14:47:19 -04:00