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Author SHA1 Message Date
Alyssa Rosenzweig
40812efaae OpcodeDispatcher: better handle SIB indexing 
if we have shift and a constant, we can save an instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
3429321d59 OpcodeDispatcher: allow upper garbage for MOVGPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
6cddd6cbe7 OpcodeDispatcher: allow upper garbage for a2/a3 
stores mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
23d07d7d0c OpcodeDispatcher: fix folding negative offsets for 32-bit 
I don't know what I was thinking when I wrote that code. Drop the silly logic
and let ConstProp inline the immediates. This fixes a lot of silly code
generated for 32-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
1351575713 InstructionCountCI: add fpemu blocks 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Ryan Houdek
8aa7d1a278
Merge pull request #3939 from alyssarosenzweig/opt/cfinv 
Invert carry flag internally
 2024-08-13 01:05:54 -07:00
Ryan Houdek
fb60a8a032
Docs: Update for release FEX-2408 2024-08-12 15:05:37 -07:00
Alyssa Rosenzweig
f40bc134df
Merge pull request #3945 from Sonicadvance1/config_nonnullable 
Config: Little assume non-null check
 2024-08-11 15:23:37 -04:00
Ryan Houdek
f3811f04bd
Config: Little assume non-null check 
Removes a simple runtime nullcheck in Config::Layer::Set. Since we never pass a
nullptr to this.
 2024-08-11 10:25:53 -07:00
Alyssa Rosenzweig
94bb7eb311
Merge pull request #3937 from Sonicadvance1/fix_script 
Scripts: Fix issue in aarch64_fit_native
 2024-08-10 20:07:43 -04:00
Alyssa Rosenzweig
3383786205 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:21:08 -04:00
Alyssa Rosenzweig
91f4c54768 OpcodeDispatcher: optimize RDRAND on flagm 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:21:08 -04:00
Alyssa Rosenzweig
d9c779289c OpcodeDispatcher: simplify RDRAND 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:18:00 -04:00
Alyssa Rosenzweig
5631ff4fd5 OpcodeDispatcher: optimize variable shifts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
34301319bf OpcodeDispatcher: optimize IncrementByCarry 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
8eac3198b6 OpcodeDispatcher: use carry increment for ADC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
832edd4da3 OpcodeDispatcher: use carry increment for SBC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
5823e74bcd OpcodeDispatcher: use increment carry for atomics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
a4545f493e OpcodeDispatcher: add IncrementByCarry helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
3b8cd44ca4 IR: add NZCVSelectIncrement 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
f138d7d9b8 OpcodeDispatcher: optimize JA/JNA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
3bb9d44bf5 OpcodeDispatcher: optimize SetCFDirect 
generally same # of instructions, but potentially fewer cycles:

old:
        "rmif x4, #63, #nzCv",
        "cfinv"

new:
        "xor x20, x4, #1",
        "rmif x20, #63, #nzCv"

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
06e6a1b19e OpcodeDispatcher: optimize logic ops 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
256d166126 OpcodeDispatcher: optimize DAA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
630285c589 OpcodeDispatcher: optimize SetPackedRFLAG 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
9621eca677 OpcodeDispatcher: fix setrflag masking 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
7eee50d929 OpcodeDispatcher: optimize mul/umul 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
1dc22e33ae OpcodeDispatcher: inline some flag calculations 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
0ef8aaebeb OpcodeDispatcher: optimize BZHI 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
d17c427e47 OpcodeDispatcher: optimize non-flagm2 comiss 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
f73fb62c6e OpcodeDispatcher: optimize V(P)TEST 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
5976b712ca OpcodeDispatcher: optimize bl* 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
63f5e64adb OpcodeDispatcher: optimize add/sub 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
34ee3bb8aa OpcodeDispatcher: optimize clc/stc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
79c745929a FEXCore: invert CF internally 
Flag day change to the ABI.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
8330cc6876 OpcodeDispatcher: defer carry inverts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:05:21 -04:00
Ryan Houdek
03ca3e7e68
Merge pull request #3934 from bylaws/wow64-b 
WOW64: Support the JIT API as used by Windows
 2024-08-10 09:07:58 -07:00
Ryan Houdek
2c3e6cbe65
Merge pull request #3932 from bylaws/arm64-callchk 
ARM64EC: Install a custom call checker to bypass NTDLL function patches
 2024-08-10 09:07:31 -07:00
Alyssa Rosenzweig
16e6163677 OpcodeDispatcher: drop unused NZCVIndexMask 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 11:26:12 -04:00
Alyssa Rosenzweig
bbbc0dc9dc OpcodeDispatcher: fix weird formatting 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 11:26:12 -04:00
Alyssa Rosenzweig
f9bdf0bd01
Merge pull request #3938 from Sonicadvance1/fix_vpblend_test 
unittests: Fixes vpblend unittest
 2024-08-10 11:08:03 -04:00
Ryan Houdek
4afc7adb05
unittests: Fixes vpblend unittest 
This typo was causing undefined data to be used in the unittest, showed
up in debug builds.
 2024-08-10 07:43:25 -07:00
Ryan Houdek
2152d1b2e9
Scripts: Fix issue in aarch64_fit_native 
Apparently I messed this up in testing, is now fixed.
 2024-08-09 21:04:26 -07:00
Ryan Houdek
0ecfc651b6
Merge pull request #3931 from Sonicadvance1/move_hostfeatures_init 
FEXCore: Pass HostFeatures in to CreateNewContext directly
 2024-08-09 20:30:17 -07:00
Ryan Houdek
4a3250ddea
Merge pull request #3928 from bylaws/winval 
InvalidationTracker: Better match Windows code invalidation behaviour
 2024-08-09 20:29:57 -07:00
Alyssa Rosenzweig
633f624a69
Merge pull request #3930 from Sonicadvance1/hostfeatures_only_harnessrunner 
HostFeatures: Removes feature flags always supported by FEX
 2024-08-09 15:12:04 -04:00
Billy Laws
26a8a2717c WOW64: Mark the CPU area context as dirty initially 
After thread creation, the WOW64 CPU area context needs to be flushed
into the FEX state before entering the JIT. Wine explicitly calls
BTCpuSetContext to trigger this but Windows doesn't.
 2024-08-09 11:57:09 +00:00
Billy Laws
4c0e6d5779 WOW64: Shift down used TLS slots 
Fixes a crash on native Windows.
 2024-08-09 11:57:09 +00:00
Billy Laws
a350ef5d1b WOW64: Match the Windows function protoypes 2024-08-09 11:57:09 +00:00
Billy Laws
9d9bd750e2 ARM64EC: Install a custom call checker to bypass NTDLL function patches 
Some programs will hook the NTDLL exports that FEX depends on, the
regular ARM64EC call checker will detect such patches and invoke the
JIT to run them, which leads to infinite recursion if those same
exports are used during code compilation. Fix this by resolving all
patchable FFSs to their native ARM implementations for all indirect
calls performed by FEX, skipping any x86 patches.
 2024-08-09 11:48:18 +00:00