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Author SHA1 Message Date
Ryan Houdek
7b70925acf
unittests/gvisor: Updates known failures test for poll 2024-08-15 00:48:57 -07:00
Ryan Houdek
2a3e0b93e8
unittests: Update syscalls_efault test 2024-08-15 00:48:57 -07:00
Ryan Houdek
2b26d0fff5
LinuxSyscalls: Implements less invasive assertion only EFAULT handlers 
With the previous Copy{To,From}User helpers we need to actually
implement the handlers correctly. We want something that is a bit
lighter so we don't need to implement the faulting path in the syscall
handlers.

Implements a handful of helpers that just check for readable and
writable capability which can be thrown in to an assertion handler that
is zero cost in release mode.

Readable is checked by just attempting to read all bytes.
Writable is checked by attempting to read each byte and writing it back
to the same location.

Uses these helpers in x64/FD.cpp to showcase how they will be used to
detect EFAULT. Tested locally that they work correctly by writing some
small tests for the syscalls that expect EFAULT.
 2024-08-15 00:48:57 -07:00
Ryan Houdek
33558e63c4
Merge pull request #3950 from alyssarosenzweig/bug/flagm-ci 
InstructionCountCI: explicitly enable flagm for multiinst
 2024-08-13 13:49:11 -07:00
Ryan Houdek
97c229d5eb
Merge pull request #3935 from bylaws/win-feats 
Windows: Support CPU feature detection from ID registry keys
 2024-08-13 13:40:54 -07:00
Billy Laws
16b007df33 Windows: Partially implement the registry read API 2024-08-13 13:31:32 +00:00
Billy Laws
3cbc421c7e Windows: Detect CPU features using the registry 
Native Windows does not support ID instruction emulation, instead it
populates registry keys containing their values.
 2024-08-13 13:31:32 +00:00
Billy Laws
890e5e1f0f FEXCore: Support disabling host cacheline clean/clear operations 2024-08-13 13:25:34 +00:00
Billy Laws
6b98454f03 HostFeatures: Split out vixl feature and CTR/MIDR detection 2024-08-13 13:25:34 +00:00
Alyssa Rosenzweig
b05329c8df InstructionCountCI: explicitly enable flagm for multiinst 
Closes: https://github.com/FEX-Emu/FEX/issues/3949
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 09:09:07 -04:00
Ryan Houdek
6f43c8ffac
Merge pull request #3947 from alyssarosenzweig/opt/littles 
Little opcodedispatcher optimizations
 2024-08-13 05:54:47 -07:00
Alyssa Rosenzweig
ffac98051f InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
40812efaae OpcodeDispatcher: better handle SIB indexing 
if we have shift and a constant, we can save an instruction

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
3429321d59 OpcodeDispatcher: allow upper garbage for MOVGPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
6cddd6cbe7 OpcodeDispatcher: allow upper garbage for a2/a3 
stores mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
23d07d7d0c OpcodeDispatcher: fix folding negative offsets for 32-bit 
I don't know what I was thinking when I wrote that code. Drop the silly logic
and let ConstProp inline the immediates. This fixes a lot of silly code
generated for 32-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Alyssa Rosenzweig
1351575713 InstructionCountCI: add fpemu blocks 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-13 08:41:16 -04:00
Ryan Houdek
8aa7d1a278
Merge pull request #3939 from alyssarosenzweig/opt/cfinv 
Invert carry flag internally
 2024-08-13 01:05:54 -07:00
Ryan Houdek
fb60a8a032
Docs: Update for release FEX-2408 2024-08-12 15:05:37 -07:00
Alyssa Rosenzweig
f40bc134df
Merge pull request #3945 from Sonicadvance1/config_nonnullable 
Config: Little assume non-null check
 2024-08-11 15:23:37 -04:00
Ryan Houdek
f3811f04bd
Config: Little assume non-null check 
Removes a simple runtime nullcheck in Config::Layer::Set. Since we never pass a
nullptr to this.
 2024-08-11 10:25:53 -07:00
Alyssa Rosenzweig
94bb7eb311
Merge pull request #3937 from Sonicadvance1/fix_script 
Scripts: Fix issue in aarch64_fit_native
 2024-08-10 20:07:43 -04:00
Alyssa Rosenzweig
3383786205 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:21:08 -04:00
Alyssa Rosenzweig
91f4c54768 OpcodeDispatcher: optimize RDRAND on flagm 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:21:08 -04:00
Alyssa Rosenzweig
d9c779289c OpcodeDispatcher: simplify RDRAND 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 15:18:00 -04:00
Alyssa Rosenzweig
5631ff4fd5 OpcodeDispatcher: optimize variable shifts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
34301319bf OpcodeDispatcher: optimize IncrementByCarry 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
8eac3198b6 OpcodeDispatcher: use carry increment for ADC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
832edd4da3 OpcodeDispatcher: use carry increment for SBC 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
5823e74bcd OpcodeDispatcher: use increment carry for atomics 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
a4545f493e OpcodeDispatcher: add IncrementByCarry helper 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
3b8cd44ca4 IR: add NZCVSelectIncrement 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:43 -04:00
Alyssa Rosenzweig
f138d7d9b8 OpcodeDispatcher: optimize JA/JNA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
3bb9d44bf5 OpcodeDispatcher: optimize SetCFDirect 
generally same # of instructions, but potentially fewer cycles:

old:
        "rmif x4, #63, #nzCv",
        "cfinv"

new:
        "xor x20, x4, #1",
        "rmif x20, #63, #nzCv"

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
06e6a1b19e OpcodeDispatcher: optimize logic ops 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
256d166126 OpcodeDispatcher: optimize DAA 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
630285c589 OpcodeDispatcher: optimize SetPackedRFLAG 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
9621eca677 OpcodeDispatcher: fix setrflag masking 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
7eee50d929 OpcodeDispatcher: optimize mul/umul 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
1dc22e33ae OpcodeDispatcher: inline some flag calculations 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
0ef8aaebeb OpcodeDispatcher: optimize BZHI 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
d17c427e47 OpcodeDispatcher: optimize non-flagm2 comiss 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
f73fb62c6e OpcodeDispatcher: optimize V(P)TEST 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
5976b712ca OpcodeDispatcher: optimize bl* 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
63f5e64adb OpcodeDispatcher: optimize add/sub 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
34ee3bb8aa OpcodeDispatcher: optimize clc/stc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
79c745929a FEXCore: invert CF internally 
Flag day change to the ABI.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:06:42 -04:00
Alyssa Rosenzweig
8330cc6876 OpcodeDispatcher: defer carry inverts 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-10 13:05:21 -04:00
Ryan Houdek
03ca3e7e68
Merge pull request #3934 from bylaws/wow64-b 
WOW64: Support the JIT API as used by Windows
 2024-08-10 09:07:58 -07:00
Ryan Houdek
2c3e6cbe65
Merge pull request #3932 from bylaws/arm64-callchk 
ARM64EC: Install a custom call checker to bypass NTDLL function patches
 2024-08-10 09:07:31 -07:00