Some of the newer CPU cores in LLVM's source claim to be a Cortex-A73,
which means they become limited to an ARMv8.0 feature set.
This is what you get if you compile FEX with -mcpu=native
To work around this issue, manually parse /proc/cpuinfo ourselves and
pull out the CPU type to pass to clang directly.
This also fixes the issue that we were using -march on AArch64, which no
longer works on newer clang versions. We instead need to use mcpu or
mtune.
Should improve all atomic op performance outside of the JITs, where they
were turning in to loadstore exclusive pairs.
Now that everything is punched through that is necessary, we can now
have IR based unit tests that will be used to ensure the IR is working
correctly.
Specifically this is necessary for quick iterating on RA testing.
This will allow us to add unit tests that have known failures like
unsupported features
Additionally if the test passes and is on the known failure list then it
still fails since its state has changed
I had to change how blocks are represented to make it easier to parse
This required a fairly substantial refactor that makes it so blocks are
represented differently and we can walk them sequentially.
This will make future analysis easier to deal with.
Had to rewrite the passes and core's parsing of the IR afterwards.
Moved RA in to a optimization pass to be shared between the JIT backends
This works because x86-64 and AArch64 RA can be identical.
Still doesn't support PHI nodes or spilling correctly, this is the first
step in the process of getting there.
Argumentless IR emitter functions were prone to generating invalid code.
Remove them from the python emitter and change the branch instructions
that were using them to a new version instead.
Adds NumUse tracking as well.
