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Author	SHA1	Message	Date
Alyssa Rosenzweig	a10f984b1c	clang-format: left-align escaped newlines ... alternative to #3638. this is theoretically better for side-by-side diffs. in practice it may make other diffs worse since all the \'s change when part of the macro change. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-20 09:47:21 -04:00
Ryan Houdek	048c8ded88	Merge pull request #3622 from Sonicadvance1/move_emitter	2024-05-17 10:41:51 -07:00
Alyssa Rosenzweig	948938bf4b	Merge pull request #3636 from alyssarosenzweig/jit/factor-vec ... JIT: factor out sub reg size conversion	2024-05-17 09:40:32 -04:00
Alyssa Rosenzweig	bb064c7334	JIT/AtomicOps: factor out elementsize ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 17:28:58 -04:00
Alyssa Rosenzweig	2d3d49b900	JIT/ConversionOps: use ConvertSubRegSize* ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 17:18:59 -04:00
Alyssa Rosenzweig	ea7096ed5b	JIT/MemoryOps: use ConvertSubRegSize8 ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 17:16:12 -04:00
Alyssa Rosenzweig	7a0f6c0a80	JIT: factor ConvertSize helper ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 17:13:00 -04:00
Alyssa Rosenzweig	e4ee35a925	JIT: factor out sub reg size conversion ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 15:56:05 -04:00
Ryan Houdek	d3ab9bdef6	Remove Float16 ... We aren't using it. We won't be using it. We need unit tests in our lives if we want this.	2024-05-16 12:06:54 -07:00
Ryan Houdek	926eefc86c	Merge pull request #3635 from alyssarosenzweig/opt/flag-store ... OpcodeDispatcher: reorder some moves	2024-05-16 10:58:40 -07:00
Ryan Houdek	3eb7a5b998	Merge pull request #3632 from pmatos/RemoveBlocks ... Use erase-remove idiom to remove element	2024-05-16 10:50:50 -07:00
Ryan Houdek	58614ff131	Merge pull request #3634 from alyssarosenzweig/constprop/leftover ... ConstProp: remove x86 jit leftover	2024-05-16 10:48:31 -07:00
Alyssa Rosenzweig	bf3a09e5e3	ConstProp: remove x86 jit leftover ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 09:21:41 -04:00
Alyssa Rosenzweig	83c536c47f	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 08:32:11 -04:00
Alyssa Rosenzweig	7b39e57e72	OpcodeDispatcher: defer overwritten store ... this can save moves, as it's a bit easier to reason about the live ranges. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-16 08:31:58 -04:00
Alyssa Rosenzweig	5bedf32666	Merge pull request #3633 from pmatos/UndefShift ... Fix left shift undefined behaviour	2024-05-16 07:45:38 -04:00
Paulo Matos	1eb7be9870	Check BitOffset instead of zeroext	2024-05-16 10:50:40 +02:00
Paulo Matos	93e4288c57	Fix left shift undefined behaviour ... Here BitOffset can have values higher than 32.	2024-05-16 10:22:03 +02:00
Paulo Matos	9ca4868833	Use erase-remove idiom to remove element ... Fixes #3631	2024-05-16 10:16:01 +02:00
Alyssa Rosenzweig	c5f8ea58e9	Merge pull request #3629 from pmatos/Unsup-typo ... NFC: Fix typo	2024-05-15 10:31:38 -04:00
Paulo Matos	5bee17bee1	NFC: Fix typo	2024-05-15 15:10:00 +02:00
Ryan Houdek	efe7c54374	Merge pull request #3625 from Sonicadvance1/restricted_inst ... FEXCore: Fixes the difference between CPL-0 and undefined instructions	2024-05-14 07:11:19 -07:00
Ryan Houdek	9e1840e974	FEXCore: Moves CodeEmitter to FHU ... Now that the vixl dependency is gone, this gets moved to FHU since the frontend is going to need it for a microjit.	2024-05-13 12:48:10 -07:00
Ryan Houdek	1f40590f9a	Emitter: Inline IsImmLogical from vixl ... The only core vixl usage we use in the emitter. Is a complete pain to reimplement so keep it around.	2024-05-13 12:48:10 -07:00
Ryan Houdek	64a3bc235d	unittests/Emitter: Ensures coverage of imm float encodings ... To ensure we round everything correctly for the new float16 class	2024-05-13 12:48:10 -07:00
Ryan Houdek	7d9af246ea	CodeEmitter: Removes vixl Float16 usage ... Creating local Float16 helper which handles our needs	2024-05-13 12:48:09 -07:00
Ryan Houdek	6d3471bcaa	Merge pull request #3627 from Sonicadvance1/timeout_merge_base ... Github: Support a timeout on checkout	2024-05-13 11:53:11 -07:00
Ryan Houdek	a8714dbd49	Github: Support a timeout on checkout ... Sometimes github or the CI runner times out trying to checkout the source and stays timing out forever. Give it a three minute timeout otherwise the CI runner will stall forever.	2024-05-13 11:26:54 -07:00
Ryan Houdek	512312fa06	FEXLinuxTests: Implements a test for the new instructions	2024-05-13 11:12:26 -07:00
Ryan Houdek	010028e381	FEXCore: Fixes the difference between CPL-0 and undefined instructions ... undefined instructions are expected to return SIGILL, while implemented instructions that aren't available in CPL-3 are expected to SIGSEGV. Noticed this while testing out CPU-Z, it installs a kernel module and does a bunch of `RDMSR` and `OUTS` instructions. Decided to walk through the rest of the instructions in the `System Instruction Reference` section. Turns out there's a bunch of oddities in there that we don't support. First step is to go through all the explicitl SIGILL and SIGSEGV and implement a test for them. Next step will be implementing the remaining operations that are considered "System" operations but are still available in CPL-3. This list includes: - lar - lgdt - lsl - sidt - sldt - stac - clac - verr - verw	2024-05-13 11:12:26 -07:00
Ryan Houdek	f27f1871e4	Merge pull request #3624 from Sonicadvance1/faulty_mc_fault_face ... FEXCore: Get rid of DeferredSignalFaultAddress and use the InterruptFaultPage	2024-05-13 03:22:43 -07:00
Ryan Houdek	3a7aa83ab1	Merge pull request #3626 from pmatos/TestClangIgnore ... Fix exec path where file needs to be ignored	2024-05-13 02:55:33 -07:00
Paulo Matos	bcc136c3b9	Fix exec path where file needs to be ignored ... Ignored files were not being checked. Both clang-format.py wrapper and code-format-helper where not aligned.	2024-05-13 11:41:44 +02:00
Ryan Houdek	3da31830d1	InstcountCI: Update	2024-05-10 15:34:13 -07:00
Ryan Houdek	d19b57a52e	FEXCore: Get rid of DeferredSignalFaultAddress and use the InterruptFaultPage ... Arm64ec introduced the InterruptFaultPage which is lower overhead since instead of ldr+str it just turns in to a single str. We were already allocating the space, FEXCore and the frontend signal delegator just needed to be updated to understand the new location. We can additionally use this in the future if we want to make deferred async signals INSIDE the JIT only cost a single str as well.	2024-05-10 15:31:28 -07:00
Ryan Houdek	ef6d640a8c	Merge pull request #3612 from Sonicadvance1/threadmanager_move ... FEXLoader: Changes frontend thread management to wrap FEXCore thread objects	2024-05-09 09:27:11 -07:00
Ryan Houdek	2cae2f2462	Merge pull request #3617 from bylaws/arm64ec-dispatcher ... FEXCore: ARM64EC x64 entry/exit support	2024-05-08 12:25:26 -07:00
Ryan Houdek	1fde5d7fca	Merge pull request #3621 from alyssarosenzweig/ra/drop-avx ... RegisterAllocationPass: drop AVX flag	2024-05-08 11:42:53 -07:00
Ryan Houdek	10de2f83ac	Merge pull request #3620 from alyssarosenzweig/ir/burn-parser ... IR: drop IRParser	2024-05-08 11:29:37 -07:00
Alyssa Rosenzweig	9d86e11a47	RegisterAllocationPass: drop AVX flag ... RA should not depend on whether we support AVX, that's a huge layering violation! and fortunately, it does not. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:26:31 -04:00
Alyssa Rosenzweig	4d503d3155	RegisterAllocationPass: drop prewritable check ... always true. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:24:41 -04:00
Alyssa Rosenzweig	7e663b91df	IR: drop IRParser ... Aside from its own self-test, the parser is unused and should remain that way, since it's a maintenance burden with no real benefit. Burn it. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:16:54 -04:00
Alyssa Rosenzweig	47242dc190	Merge pull request #3616 from alyssarosenzweig/sra/simplify-1 ... SRA controlled burn	2024-05-08 14:10:48 -04:00
Alyssa Rosenzweig	e13c8e3295	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig	3c3ba62c10	MemoryOps: optimize 32-bit SRA case ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig	34fe56dfb2	DeadStoreElimination: CSE block info ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig	ecf8cde5e0	DeadStoreElimination: group common logic ... slightly less obnoxious copypaste. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig	55284aad7e	DeadStoreElimination: don't handle partial stores ... SRA replaces the whole contents of the destination. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig	3afc35f7b4	DeadStoreElimination: simplify ... use registers internally, not synthesized offsets Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig	1058428a51	IR: document invariant on SRA ... This lets us simplify a lot! Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-05-08 14:01:42 -04:00