Tony Wasserka
b9829ed316
OpcodeDispatcher: Replace even more hand-written wrapper templates
2024-07-11 16:19:15 +02:00
Tony Wasserka
4ccec17676
OpcodeDispatcher: Replace more hand-written wrapper templates
2024-07-11 16:19:15 +02:00
Tony Wasserka
f45082043b
OpcodeDispatcher: Replace hand-written wrapper templates with a generic utility
2024-07-11 16:19:14 +02:00
Tony Wasserka
3222f13dde
Fix comment formatting
2024-07-11 16:19:14 +02:00
Mai
b282620a48
Merge pull request #3857 from Sonicadvance1/sve_bitperm
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Arm64: Implement support for SVE bitperm
2024-07-11 05:05:41 -04:00
Ryan Houdek
3ff1ff8f74
InstcountCI: Update for svebitperm
2024-07-11 01:46:35 -07:00
Ryan Houdek
e24b01b6cb
Arm64: Implement support for SVE bitperm
2024-07-11 01:46:35 -07:00
Tony Wasserka
9a8694c2f3
Merge pull request #3853 from neobrain/refactor_warn_fixes
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Fix all the warnings
2024-07-11 10:12:41 +02:00
Tony Wasserka
070a9148aa
Merge pull request #3852 from neobrain/refactor_opdispatch_codesize
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OpcodeDispatcher: Avoid template monomorphization to reduce FEXLoader binary size
2024-07-11 09:58:49 +02:00
Tony Wasserka
f19fe3b6f3
Fix warning about an expression with side effects being passed to __builtin_assume
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LOGMAN_THROW_AA_FMT has no benefit over LOGMAN_THROW_A_FMT here, so just use
the latter.
2024-07-11 09:54:31 +02:00
Tony Wasserka
8d2b15665d
Fix unused-variable warnings
2024-07-11 09:54:30 +02:00
Tony Wasserka
4dec8f22f8
Fix packed-non-pod warnings
2024-07-11 09:54:30 +02:00
Tony Wasserka
a39b3aca78
Fix invalid-offsetof warnings due to JsonAllocator not being standard layout
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Inheritance can be used here instead, which allows the JsonAllocator to be
reconstructed using a downcast.
2024-07-11 09:54:30 +02:00
Tony Wasserka
5dc4ab062d
Fix invalid-offsetof warnings due to InternalThreadState not being standard layout
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See https://github.com/llvm/llvm-project/issues/53021 for more information
about unique_ptr turning non-standard-layout.
2024-07-11 09:54:30 +02:00
Ryan Houdek
31f82c1d96
InstcountCI: Update for SVE NT load support
2024-07-10 23:07:58 -07:00
Ryan Houdek
548fd9daf8
OpcodeDispatcher: Implement support for SSE4.1 NT load
2024-07-10 23:07:37 -07:00
Ryan Houdek
f831f5a0e1
AVX128: Implement support for NT Load
2024-07-10 23:07:14 -07:00
Ryan Houdek
4c21aa2604
Arm64: Implement support for NT Loads with ASIMD fallback
2024-07-10 23:06:46 -07:00
Ryan Houdek
c9efb75714
CodeEmitter: Implement support for SVE NT loads
2024-07-10 23:06:19 -07:00
Ryan Houdek
5e56bdc0fd
InstcountCI: Add support for SVE bitperm
2024-07-10 21:48:37 -07:00
Ryan Houdek
3554d5c2f7
HostFeatures: Check for SVE bit permute extension
2024-07-10 21:45:07 -07:00
Mai
5fe405e1fb
Merge pull request #3855 from neobrain/fix_aotir_uniqueptr
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AOTIR: Change std::unique_ptr to fextl::unique_ptr
2024-07-10 17:04:12 -04:00
Tony Wasserka
8381d44bbd
Merge pull request #3854 from neobrain/fix_default_delete
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fextl: Properly handle nullptr arguments in fextl::default_delete
2024-07-10 23:00:52 +02:00
Tony Wasserka
56bb3744a5
AOTIR: Change std::unique_ptr to fextl::unique_ptr
2024-07-10 19:34:24 +02:00
Tony Wasserka
470b435afd
fextl: Properly handle nullptr arguments in fextl::default_delete
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This reflects behavior of std::default_delete.
2024-07-10 19:17:50 +02:00
Alyssa Rosenzweig
a4f8bbff02
OpcodeDispatcher: reg cache avx high
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
cf5ab05b90
OpcodeDispatcher: reg cache AbridgedFTW
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
3a2ce240f9
OpcodeDispatcher: reg cache DF
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
1f01dd53f7
OpcodeDispatcher: reg cache fprs
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
72d41d70b6
OpcodeDispatcher: introduce GPR-only reg cache
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
42b5b1f64c
Core: partially flush register cache per instruction
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This will mitigate problems later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
2949bc211d
OpcodeDispatcher: thunk through FlushRegisterCache
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:36:18 -04:00
Alyssa Rosenzweig
5e0952159d
unittests: add test for a MMX register cache bug
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this failed on an earlier version of the register cache.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-10 11:34:24 -04:00
Tony Wasserka
441187470e
OpcodeDispatcher: Avoid monomorphization of some AVX functions
2024-07-10 17:01:30 +02:00
Tony Wasserka
59fd13cc2f
OpcodeDispatcher: Avoid monomorphization of even more functions
2024-07-10 17:01:30 +02:00
Tony Wasserka
c9e7bfdf16
OpcodeDispatcher: Avoid monomorphization of more functions
2024-07-10 17:01:30 +02:00
Tony Wasserka
2d700c381e
OpcodeDispatcher: Avoid monomorphization of large functions
2024-07-10 17:01:30 +02:00
Ryan Houdek
72d6c8ebd6
Merge pull request #3820 from alyssarosenzweig/ir/drop-deferred
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Drop deferred flag infrastructure
2024-07-09 17:06:25 -07:00
Ryan Houdek
991c6941c1
Merge pull request #3849 from alyssarosenzweig/ir/drop-parser-2
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Scripts: drop remnant of IR parser
2024-07-09 16:48:36 -07:00
Alyssa Rosenzweig
f974696e34
Scripts: drop remnant of IR parser
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unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-07-09 16:08:38 -04:00
Alyssa Rosenzweig
3ef9ea94e5
Merge pull request #3848 from pmatos/FTSTX87Tests
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Tests for X87 FTST
2024-07-09 09:10:29 -04:00
Paulo Matos
381ce23fd7
Tests for X87 FTST
2024-07-09 13:36:16 +02:00
Mai
af6a0be832
Merge pull request #3842 from Sonicadvance1/fix_f64_to_i32
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VCVT{T,}PD2DQ fixes and optimization
2024-07-09 03:49:31 -04:00
Ryan Houdek
287fe5beac
InstcountCI: Update
2024-07-09 00:38:48 -07:00
Ryan Houdek
b9c214e6e8
OpcodeDispatcher: Use new IR op for vcvt{t,}pd2dq
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Also fixes a bug where it was failing to zero the upper bits of the
destination register in the AVX128 implementation. Which the updated
unit tests now check against.
Fixes a minor precision issue that was reported in #2995 . We still don't
return correct values for overflow. x86 always returns maximum negative
int32_t on overflow, ARM will return maximum negative or positive
depending on sign of the double.
2024-07-09 00:38:47 -07:00
Ryan Houdek
d3d76aa8ce
IR: Adds new F64 -> I32 operation that changes behaviour depending on SVE
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SVE added the ability to do F64 -> I32 conversions directly without an
fcvtn inbetween. So maybe sure to support them.
2024-07-09 00:38:47 -07:00
Ryan Houdek
3bea08da5f
Merge pull request #3843 from Sonicadvance1/remove_half_moves_fma3
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Arm64: Remove one move if possible in FMA operations
2024-07-09 00:25:07 -07:00
Paulo Matos
3d5cacbdc3
Enable coverage configuration for FEX
2024-07-09 08:03:41 +02:00
Mai
7ccb252069
Merge pull request #3837 from Sonicadvance1/optimize_sve_vpgatherdq
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AVX128: Extends 32-bit indexes path for 128-bit operations
2024-07-08 22:01:02 -04:00
Ryan Houdek
31547462bb
InstcountCI: Update for final SVE AVX128 improvements.
2024-07-08 18:44:07 -07:00
