Paulo Matos
06b950a9cd
Rounding test doesn't need to be skipped
2024-11-04 19:02:12 +01:00
Paulo Matos
de70651406
Add some more tests as unsupported by vixl
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It seems a form of `mrs` is unsupported as well as the hint `wfe` used for `pause`.
Remove skipping Rounding(Neg|Pos).asm as they are passing.
2024-11-04 18:52:48 +01:00
Ryan Houdek
96fa2ad8eb
InstcountCI: Update
2024-10-25 15:43:10 -07:00
Ryan Houdek
51fa61a1cd
InstcountCI: Adds missing pushf implementations
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pushf was aliasing to pushfq, needed an o16 prefix.
We also weren't testing the 32-bit path, which only exists on 32-bit, so
add that as well.
2024-10-25 15:40:44 -07:00
Paulo Matos
11a87c22f9
instcountci: X87 code simplification
2024-10-24 18:17:48 +02:00
Ryan Houdek
caaacb6c15
Merge pull request #4127 from alyssarosenzweig/opt/masking
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Build + Test / build_plus_test ([self-hosted ARMv8.0]) (push) Waiting to run
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Hostrunner tests / hostrunner_tests ([self-hosted x64]) (push) Waiting to run
Instruction Count CI run / instcountci_tests ([self-hosted ARM64]) (push) Waiting to run
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Mingw build / mingw_build ([self-hosted ARM64 mingw]) (push) Waiting to run
Mingw build / mingw_build ([self-hosted ARM64EC mingw ARM64]) (push) Waiting to run
Vixl Simulator run / vixl_simulator ([self-hosted ARMv8.4]) (push) Waiting to run
Vixl Simulator run / vixl_simulator ([self-hosted x64]) (push) Waiting to run
Optimize bsf, bsr, register cmpxchg, pcmpistri
2024-10-23 07:28:29 -07:00
Paulo Matos
dc93e30451
Disable RPRES in instcounci files
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This was giving false changes on RPRES enabled HW.
2024-10-23 15:09:17 +02:00
Alyssa Rosenzweig
d2a42c0038
InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-10-22 13:39:21 -04:00
Ryan Houdek
ddcca58f64
InstcountCI: Update for PSHUF{L,H}W changes
2024-10-21 09:25:58 -07:00
Ryan Houdek
8b7a227820
InstcountCI: Update
2024-10-18 15:49:25 -07:00
Ryan Houdek
d7afcee622
AVX128: Fixes asome AVX bugs
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vblendvps, vblendvpd, vpblendvb all broke because of failing to zext the
128-bit register correctly.
vinsertps broke because it was accidentally using the wrong
implementation.
Extends each of their unittests to handle these cases.
2024-10-18 15:49:25 -07:00
Paulo Matos
5997030c97
instcountci: Fix FXTRACT for 0.0 and -0.0
2024-10-17 09:13:40 +02:00
Paulo Matos
3c8086373b
FXTRACT fix ASM tests
2024-10-17 09:05:17 +02:00
Ryan Houdek
0897cd8777
Merge pull request #4116 from Sonicadvance1/personality_handling
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Build + Test / build_plus_test ([self-hosted ARMv8.0]) (push) Waiting to run
Build + Test / build_plus_test ([self-hosted ARMv8.2]) (push) Waiting to run
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Hostrunner tests / hostrunner_tests ([self-hosted x64]) (push) Waiting to run
Instruction Count CI run / instcountci_tests ([self-hosted ARM64]) (push) Waiting to run
Instruction Count CI run / instcountci_tests ([self-hosted x64]) (push) Waiting to run
Mingw build / mingw_build ([self-hosted ARM64 mingw]) (push) Waiting to run
Mingw build / mingw_build ([self-hosted ARM64EC mingw ARM64]) (push) Waiting to run
Vixl Simulator run / vixl_simulator ([self-hosted ARMv8.4]) (push) Waiting to run
Vixl Simulator run / vixl_simulator ([self-hosted x64]) (push) Waiting to run
LinuxEmulation: Personality handling
2024-10-16 15:52:35 -07:00
Ryan Houdek
4b945a9041
Merge pull request #4105 from pmatos/X87MMXState
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Implement explicit state switch between X87 and MMX
2024-10-16 15:52:27 -07:00
Ryan Houdek
d66ed71bc6
Merge pull request #4082 from Sonicadvance1/fix_wine
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FEXLoader: Fixes newer wine versions and Fedora
2024-10-16 15:52:19 -07:00
LC
b5b34df155
Merge pull request #4119 from Sonicadvance1/unaligned_lock
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Build + Test / build_plus_test ([self-hosted ARMv8.0]) (push) Has been cancelled
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Build + Test / build_plus_test ([self-hosted ARMv8.4]) (push) Has been cancelled
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Instruction Count CI run / instcountci_tests ([self-hosted ARM64]) (push) Has been cancelled
Instruction Count CI run / instcountci_tests ([self-hosted x64]) (push) Has been cancelled
Mingw build / mingw_build ([self-hosted ARM64 mingw]) (push) Has been cancelled
Mingw build / mingw_build ([self-hosted ARM64EC mingw ARM64]) (push) Has been cancelled
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Vixl Simulator run / vixl_simulator ([self-hosted x64]) (push) Has been cancelled
unittests/ASM: Adds missing unaligned atomic tests
2024-10-15 12:16:37 -04:00
Paulo Matos
def561986b
instcountci: Implements explicit state switch between X87 and MMX
2024-10-15 17:58:59 +02:00
Paulo Matos
5c258d4a2a
ASM Test: Implements explicit state switch between X87 and MMX
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Tags is set to all valid in FEX, but in host it's set to all valid _and_
reinterpreted. Adding this to known failures in the host runner.
2024-10-15 17:58:59 +02:00
Ryan Houdek
4f03044fe7
unittests/ASM: Adds missing unaligned atomic tests
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Fixes #2670
Walked through all the unaligned atomic tests to find which ones were
missing. Turns out it was only ADC, NEG, NOT, and SBB.
2024-10-15 06:59:38 -07:00
Ryan Houdek
b967538435
InstcountCI: Add pause instruction
2024-10-15 05:52:41 -07:00
Paulo Matos
09cb4f5fc5
Remove file since FXAM_Simple is not a Linux test
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Already properly skipped in the right place.
File added accidentally.
2024-10-11 16:55:07 +02:00
Paulo Matos
ddd7a550e4
Remove check on top 16bits
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Makes it uniform among all 3DNow tests instead of
some checking and some don't.
2024-10-11 16:18:43 +02:00
Ryan Houdek
3398f22c16
FEXLinuxTests: Adds personality test
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These would have failed before the prior changes.
2024-10-11 05:03:28 -07:00
Ryan Houdek
1365aa8881
FEXLinuxTests: Update to c++20
2024-10-11 04:52:21 -07:00
Ryan Houdek
6f096e7c4b
FHU: Add StringArgumentParser function
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Split this out so we can unittest it.
Adds a unittest to handle specific edge cases.
2024-10-11 01:40:36 -07:00
LC
c00f7813a2
Merge pull request #4108 from Sonicadvance1/ensure_x87_size_save_restore
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unittests/ASM: Ensures FNSAVE and FRSTOR only store as much data as required
2024-10-10 01:00:54 -04:00
Ryan Houdek
7c6444c37c
unitests/ASM: Removes unused MemoryRegion configs
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FEX's ASM unitests had the problem that they were copy and pasted
templates and MemoryRegion was copied in to almost all tests.
Very few tests actually use the MemoryRegion they were asking for and
instead used none, or the hardcoded memory regions that the
TestHarnessRunner provides.
This is entirely a sed replacement and minor fixups plus reverts for the
few tests that actually use the region asked for.
2024-10-08 16:07:25 -07:00
Ryan Houdek
0bb0f9cec7
unittests/ASM: Ensures FNSAVE and FRSTOR only store as much data as required
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The instruction definition only allows these instructions to load/store
94 or 108 bytes, not affecting any bytes afterwards. This is a bit
awkward because 80-bit x87 registers are stored at the end.
FEX has an optimization today where it uses overlapping loads and stores
for the first seven x87 registers, and a split loadstore for the final
register. This ensures that we get the correct data while reducing the
number of loadstores.
We didn't have a unittest in place to ensure we only ever write the
correct amount of data, so changes like in #4107 which look correct from
an initial glance, would have resulted in broken behaviour.
This unittest ensures both that the instructions don't try to access
beyond the end of the page, and also ensures that they don't overwrite
subsequent data. Making sure that potentially broken behaviour doesn't
make its way in.
2024-10-08 15:31:36 -07:00
Ryan Houdek
e82d2c70c3
Merge pull request #4095 from alyssarosenzweig/opt/jit-time
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Build + Test / build_plus_test ([self-hosted ARMv8.0]) (push) Has been cancelled
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Hostrunner tests / hostrunner_tests ([self-hosted x64]) (push) Has been cancelled
Instruction Count CI run / instcountci_tests ([self-hosted ARM64]) (push) Has been cancelled
Instruction Count CI run / instcountci_tests ([self-hosted x64]) (push) Has been cancelled
Mingw build / mingw_build ([self-hosted ARM64 mingw]) (push) Has been cancelled
Mingw build / mingw_build ([self-hosted ARM64EC mingw ARM64]) (push) Has been cancelled
Vixl Simulator run / vixl_simulator ([self-hosted ARMv8.4]) (push) Has been cancelled
Vixl Simulator run / vixl_simulator ([self-hosted x64]) (push) Has been cancelled
speed up the JIT
2024-10-04 09:00:03 -07:00
Ryan Houdek
407dc5d4dd
unittests: Adds TLS vector element loadstore test
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Hits all the instructions that would have previously crashed.
2024-10-03 20:53:28 -07:00
Ryan Houdek
16869d8954
unittests: fprem tests work since 688af49485
2024-10-03 14:03:51 -07:00
Ryan Houdek
e353ae8408
unittests: Adds x87 fprem test
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Exposes a bug in FEX's x87 FPREM implementation.
2024-10-03 14:03:51 -07:00
Alyssa Rosenzweig
44484a7b05
ConstProp: drop non-loadbearing opts
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every pattern costs us JIT time, but not every pattern is doing anything.
especially with the flag rework of 2023-2024, a lot of patterns just don't make
sense anymore. constant folding in particular isn't too useful now.
only instcountci change is AAD which i'm contractually forbidden from caring
about.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-10-02 14:01:32 -04:00
Ryan Houdek
49de1fac59
Merge pull request #4028 from neobrain/refactor_jemallocless_tools
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Build host tools without jemalloc
2024-09-30 11:59:45 -07:00
Tony Wasserka
682b8ef705
Build host tools without jemalloc
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Jemalloc blocks use on platforms with 16K pages.
2024-09-30 20:38:24 +02:00
Ryan Houdek
ee5c6af868
unittests: Be more strict with -- separator
2024-09-30 11:30:56 -07:00
Paulo Matos
f35a212f06
Fix FScale'ing zero that should return zero
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Added tests will fail without the current patch.
This will properly check if we return the correct sign of zero.
2024-09-26 17:57:39 +02:00
Alyssa Rosenzweig
598b99fe58
InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-22 14:06:27 -04:00
Alyssa Rosenzweig
9dda76ebe6
unittests: add min/max tests
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we had a bug with max of nans. since x86 behaviour is weird, add a unit test to
try all the weird things. this fails on main without AFP
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-22 14:06:27 -04:00
Ryan Houdek
88e3164b55
unittests: Fixes incorrect argument
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Turns out our unittests have been passing an incorrect argument for
years.
2024-09-14 23:15:52 -07:00
Ryan Houdek
ae9db336e7
FEXCore/Context: Removes unused features
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No functional change here.
- CoreRunningMode enum and variable wasn't used anymore.
- Code was moved to the frontend
- CustomCPUFactory wasn't used anymore
- All special signal handling and various features were moved to
TestHarnessRunner
- We also don't want to support actual custom CPU cores.
- TestHarnessRunner just runs as a host runner if compiled on an
x86-64 device if vixl sim isn't enabled now.
- Removes the Core config option entirely.
- Moves VDSOPointers struct to the frontend
- Every use of this lives in the Linux frontend instead now
2024-09-09 18:38:33 -07:00
Ryan Houdek
0a32ba9b29
instcountCI: Fixes for shifts
2024-09-08 18:03:20 -07:00
Ryan Houdek
f51832ca6b
FEXCore: Fixes a bug with VPSRLDQ/VPSLLDQ with >= 16-byte shifts
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When the shift amount is >= 16-bytes then we need to zero the register.
We had a bug where we were assigning `Result.High` to itself, which
effectively made the top 128-bits of the ymm register not modify itself.
Adds a unit test to ensure that doesn't happen again.
2024-09-08 15:39:22 -07:00
Ryan Houdek
36e4f9a070
Merge pull request #4049 from alyssarosenzweig/opt/constprop-merges
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ConstProp: speed it up
2024-09-08 10:13:23 -07:00
Alyssa Rosenzweig
2b0041a291
InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-08 10:27:20 -04:00
Alyssa Rosenzweig
46f36dc89d
InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-07 10:59:41 -04:00
Alyssa Rosenzweig
9fe7bc5818
InstCountCI: add ucomiss+pf opt case
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-07 08:26:04 -04:00
Alyssa Rosenzweig
5a590a9b11
InstCountCI: add 8-bit test cases
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-07 08:26:04 -04:00
Ryan Houdek
ca8f347902
InstcountCI: Skip rdtsc and rdtscp
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These will differ depending on which runner they are running on. Just
disable them but keep the instructions around so show how bad rdtscp is,
but how good rdtsc is.
2024-09-03 13:50:43 -07:00