Ryan Houdek
d3ab9bdef6
Remove Float16
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We aren't using it. We won't be using it. We need unit tests in our
lives if we want this.
2024-05-16 12:06:54 -07:00
Ryan Houdek
9e1840e974
FEXCore: Moves CodeEmitter to FHU
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Now that the vixl dependency is gone, this gets moved to FHU since the
frontend is going to need it for a microjit.
2024-05-13 12:48:10 -07:00
Ryan Houdek
1f40590f9a
Emitter: Inline IsImmLogical from vixl
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The only core vixl usage we use in the emitter. Is a complete pain to
reimplement so keep it around.
2024-05-13 12:48:10 -07:00
Ryan Houdek
64a3bc235d
unittests/Emitter: Ensures coverage of imm float encodings
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To ensure we round everything correctly for the new float16 class
2024-05-13 12:48:10 -07:00
Ryan Houdek
7d9af246ea
CodeEmitter: Removes vixl Float16 usage
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Creating local Float16 helper which handles our needs
2024-05-13 12:48:09 -07:00
Ryan Houdek
6d3471bcaa
Merge pull request #3627 from Sonicadvance1/timeout_merge_base
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Github: Support a timeout on checkout
2024-05-13 11:53:11 -07:00
Ryan Houdek
a8714dbd49
Github: Support a timeout on checkout
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Sometimes github or the CI runner times out trying to checkout the
source and stays timing out forever.
Give it a three minute timeout otherwise the CI runner will stall
forever.
2024-05-13 11:26:54 -07:00
Ryan Houdek
f27f1871e4
Merge pull request #3624 from Sonicadvance1/faulty_mc_fault_face
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FEXCore: Get rid of DeferredSignalFaultAddress and use the InterruptFaultPage
2024-05-13 03:22:43 -07:00
Ryan Houdek
3a7aa83ab1
Merge pull request #3626 from pmatos/TestClangIgnore
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Fix exec path where file needs to be ignored
2024-05-13 02:55:33 -07:00
Paulo Matos
bcc136c3b9
Fix exec path where file needs to be ignored
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Ignored files were not being checked. Both clang-format.py wrapper
and code-format-helper where not aligned.
2024-05-13 11:41:44 +02:00
Ryan Houdek
3da31830d1
InstcountCI: Update
2024-05-10 15:34:13 -07:00
Ryan Houdek
d19b57a52e
FEXCore: Get rid of DeferredSignalFaultAddress and use the InterruptFaultPage
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Arm64ec introduced the InterruptFaultPage which is lower overhead since
instead of ldr+str it just turns in to a single str. We were already
allocating the space, FEXCore and the frontend signal delegator just
needed to be updated to understand the new location.
We can additionally use this in the future if we want to make deferred
async signals INSIDE the JIT only cost a single str as well.
2024-05-10 15:31:28 -07:00
Ryan Houdek
ef6d640a8c
Merge pull request #3612 from Sonicadvance1/threadmanager_move
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FEXLoader: Changes frontend thread management to wrap FEXCore thread objects
2024-05-09 09:27:11 -07:00
Ryan Houdek
2cae2f2462
Merge pull request #3617 from bylaws/arm64ec-dispatcher
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FEXCore: ARM64EC x64 entry/exit support
2024-05-08 12:25:26 -07:00
Ryan Houdek
1fde5d7fca
Merge pull request #3621 from alyssarosenzweig/ra/drop-avx
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RegisterAllocationPass: drop AVX flag
2024-05-08 11:42:53 -07:00
Ryan Houdek
10de2f83ac
Merge pull request #3620 from alyssarosenzweig/ir/burn-parser
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IR: drop IRParser
2024-05-08 11:29:37 -07:00
Alyssa Rosenzweig
9d86e11a47
RegisterAllocationPass: drop AVX flag
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RA should not depend on whether we support AVX, that's a huge layering
violation! and fortunately, it does not.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:26:31 -04:00
Alyssa Rosenzweig
4d503d3155
RegisterAllocationPass: drop prewritable check
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always true.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:24:41 -04:00
Alyssa Rosenzweig
7e663b91df
IR: drop IRParser
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Aside from its own self-test, the parser is unused and should remain that way,
since it's a maintenance burden with no real benefit. Burn it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:16:54 -04:00
Alyssa Rosenzweig
47242dc190
Merge pull request #3616 from alyssarosenzweig/sra/simplify-1
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SRA controlled burn
2024-05-08 14:10:48 -04:00
Alyssa Rosenzweig
e13c8e3295
InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
3c3ba62c10
MemoryOps: optimize 32-bit SRA case
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
34fe56dfb2
DeadStoreElimination: CSE block info
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
ecf8cde5e0
DeadStoreElimination: group common logic
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slightly less obnoxious copypaste.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
55284aad7e
DeadStoreElimination: don't handle partial stores
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SRA replaces the whole contents of the destination.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
3afc35f7b4
DeadStoreElimination: simplify
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use registers internally, not synthesized offsets
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
1058428a51
IR: document invariant on SRA
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This lets us simplify a lot!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
a2fc51fc7b
IR: specify registers, not offsets for SRA
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SRA is fundamentally about hardware registers, not stores into a
software-defined context. So, it should take a register instead of an offset.
This makes all the unaligned special cases unrepresentable (by design).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
1848629ba5
RegisterAllocationPass: drop aliasable check
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always true with the new ir invariants.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
3399577330
JIT: clean up fpr sra
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
18bfc8afd0
JIT: clean up gpr sra handling
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
76b023ed3e
JIT: drop unaligned and partial SRA handling
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This is all dead, assert as much so it stays that way.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
b91b0e9d65
IR: infer SRA static class
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no need to stick it in the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Alyssa Rosenzweig
74489a4177
IR: remove dead SRA flags
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I don't know what these were meant for, and I don't care (-:
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-05-08 14:01:42 -04:00
Ryan Houdek
55d1d6bcd4
Merge pull request #3615 from bylaws/wow64-fix
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Fix WOW64 frontend with recent wine versions
2024-05-07 22:35:32 -07:00
Ryan Houdek
cd249e2c3a
Merge pull request #3614 from Sonicadvance1/remove_temporary_allocation
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FEXServer: Removes temporary variable allocation
2024-05-07 22:35:23 -07:00
Billy Laws
61cd835754
Update InstCountCI
2024-05-06 17:37:43 +00:00
Billy Laws
bd24364c1b
FEXCore: Switch stacks before exiting the JIT on ARM64EC
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This removes the need for the frontend to have any knowledge of FEX's
SRA layout.
2024-05-06 15:41:34 +00:00
Billy Laws
ab516d7b79
Dispatcher: Implement ARM64EC SRA setup entrypoints
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While the ARM64EC ABI mostly matches FEX's SRA, the stack still needs to
be switched to the emulator stack and target RIP stored into the FEX
context before jumping to the dispatcher loop.
2024-05-06 15:41:34 +00:00
Billy Laws
d25ed4b0bf
Dispatcher: Block system call callbacks when compiling code
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These callbacks are used for code invalidation and setting the right
emulated CPU features, neither of which are necessary for syscalls made
from within FEX. Avoid calling them to prevent deadlocks caused by
nested locks during compilation.
2024-05-06 15:41:28 +00:00
Billy Laws
c521d2b48d
WOW64: Support unwinding past FEX from within syscall handlers
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This is required by recent wine changes to use longjmp for user
callbacks. Switch to saving the context at every simulate call and
setting the unwind SP/PC to that context with a small SEH trampoline
for the syscall handler.
2024-05-06 15:26:36 +00:00
Billy Laws
9ed8165405
WOW64: Dynamically allocate unixcall/syscall entrypoints
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Removes the requirement that FEX needs to be loaded as part of the lower
32-bit address space.
2024-05-06 14:55:59 +00:00
Ryan Houdek
5099b2b5dc
FEXServer: Removes temporary variable allocation
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Was causing unnecessary memory allocation churn when a FEXInterpreter
was asking for the rootfs folder path.
2024-05-05 14:11:26 -07:00
Ryan Houdek
d372552593
FEXLoader: Changes frontend thread management to wrap FEXCore thread objects
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A bit of refactoring necessary before we can move the remaining Linux
specific code to the frontend.
Most of this taken from #3535 but attempting to be NFC as much as
possible.
2024-05-05 07:43:09 -07:00
Ryan Houdek
729e32ccc2
Linux: Move ThreadManager to its own header
2024-05-05 06:32:59 -07:00
Mai
170204d6f1
Merge pull request #3609 from neobrain/fix_catch2_setting
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CMake: Remove obsolete Catch2 setting
2024-05-04 00:04:52 -04:00
Mai
f7bfecd3f1
Merge pull request #3610 from Sonicadvance1/support_oryon_named
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CPUID: Adds Qualcomm Oryon product name
2024-05-04 00:04:29 -04:00
Ryan Houdek
5f0427c253
CPUID: Adds Qualcomm Oryon product name
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From https://github.com/llvm/llvm-project/pull/91022
Easy enough
2024-05-03 20:16:46 -07:00
Tony Wasserka
472860a840
CMake: Remove obsolete Catch2 setting
2024-05-03 15:25:42 +02:00
Mai
eddb7d12cc
Merge pull request #3608 from Sonicadvance1/readme_remove_x86
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Readme: Remove misleading text about x86 hosts being supported
2024-05-03 00:04:53 -04:00
