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Author	SHA1	Message	Date
Ryan Houdek	d3d76aa8ce	IR: Adds new F64 -> I32 operation that changes behaviour depending on SVE ... SVE added the ability to do F64 -> I32 conversions directly without an fcvtn inbetween. So maybe sure to support them.	2024-07-09 00:38:47 -07:00
Ryan Houdek	c9c163cd7b	unittests: Update vcv{t,tt}pd2dq tests to ensure upper bits of destination are cleared	2024-07-08 03:30:10 -07:00
Ryan Houdek	968d5e0d8f	Merge pull request #3774 from bylaws/win-ci ... FEXCore ARM64EC CI support	2024-07-06 18:22:57 -07:00
Ryan Houdek	635182b57c	Merge pull request #3832 from bylaws/wow64-wine ... WOW64: Mark the FEX dll as a wine builtin	2024-07-06 17:58:00 -07:00
Ryan Houdek	9d0b6ce75e	Merge pull request #3835 from bylaws/ec-topdown ... AllocatorHooks: Allocate from the top down on windows	2024-07-06 17:40:36 -07:00
Ryan Houdek	2fdd80fe3a	Merge pull request #3833 from bylaws/common-tso ... Windows: Commonise TSOHandlerConfig	2024-07-06 17:38:45 -07:00
Ryan Houdek	dbac23b749	Merge pull request #3834 from bylaws/ec-amd64 ... Windows: Report as an AMD64 processor when targeting ARM64EC	2024-07-06 17:38:13 -07:00
Billy Laws	7fa7061aa5	Windows: Report as an AMD64 processor when targeting ARM64EC	2024-07-06 20:37:15 +00:00
Billy Laws	e45e631199	AllocatorHooks: Allocate from the top down on windows ... FEX allocations can get in the way of allocations that are 4gb-limited even in 65-bit mode (i.e. those from LuaJIT), so allocate starting from the top of the AS to prevent conflicts.	2024-07-06 20:35:38 +00:00
Billy Laws	b21e77c1e0	Windows: Commonise TSOHandlerConfig	2024-07-06 19:20:49 +00:00
Billy Laws	ba33294225	WOW64: Mark the FEX dll as a wine builtin ... Allows it to be automatically picked up by wine during prefix setup, without a manual dll override. Thanks to AndreRH for pointing me to this.	2024-07-06 19:19:36 +00:00
Billy Laws	97c21cc3a7	CI: Add ARM64EC build CI	2024-07-06 17:27:41 +01:00
Billy Laws	7d7e6f5326	CMake: Disable WOW64 module for ARM64EC	2024-07-06 17:27:41 +01:00
Billy Laws	5e15bd935e	CMake: Disable glibc jemalloc for MinGW builds	2024-07-06 17:27:41 +01:00
Ryan Houdek	9bad09c45f	Merge pull request #3823 from alyssarosenzweig/bug/shl-var-small ... Fix CF with small shifts	2024-07-06 01:33:57 -07:00
Ryan Houdek	47d077ff22	Merge pull request #3825 from Sonicadvance1/scale_64bit_gather ... AVX128: Prescale addresses in gathers if possible	2024-07-05 19:10:43 -07:00
Ryan Houdek	bbf8dde3ca	Merge pull request #3824 from alyssarosenzweig/bug/rc2 ... OpcodeDispatcher: Fix 8/16-bit rcr masking	2024-07-05 17:01:16 -07:00
Ryan Houdek	6e8ca3bc6c	InstcountCI: Update for gather prescaling	2024-07-05 16:47:11 -07:00
Ryan Houdek	11a494d7b3	AVX128: Prescale addresses in gathers if possible ... If the host supports SVE128, if the address element size and data size is 64-bit, and the scale is not one of the two that is supported by SVE; Then prescale the addresses. 64-bit address overflow masks the top bits so is well defined that we can scale the vector elements and still execute the SVE code path in that case. Removing the ASIMD code paths from a lot of gathers. Fixes #3805	2024-07-05 16:47:11 -07:00
Alyssa Rosenzweig	9b570de33f	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 18:44:21 -04:00
Ryan Houdek	b67343fc5a	unittests: Adds a test for small shift flags calculation ... Currently we calculate CF incorrectly in the case of small shifts with large offsets.	2024-07-05 18:38:12 -04:00
Alyssa Rosenzweig	5a3c0eb83c	OpcodeDispatcher: fix shl with 8/16-bit variable ... the special case here lines up with the special case of using a larger shift for a smaller result, so we can just grab CF from the larger result. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 18:38:12 -04:00
Alyssa Rosenzweig	10391608a0	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 18:34:18 -04:00
Ryan Houdek	51c57cc5ae	unittests: More rotate with carry unit tests ... Looks like we missed some edge cases with small carry rotate. Adds even more unit tests.	2024-07-05 18:34:18 -04:00
Alyssa Rosenzweig	05e4678e65	OpcodeDispatcher: fix missing masking on smaller RCR ... I probably broke this when working on eliminating crossblock liveness. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 18:34:18 -04:00
Alyssa Rosenzweig	0f0e402db4	OpcodeDispatcher: fix CF with 8/16-bit immediate ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 18:24:34 -04:00
Ryan Houdek	653bf04db0	Merge pull request #3819 from alyssarosenzweig/bug/rcr-smol ... Fix 8/16-bit RCR	2024-07-05 12:49:23 -07:00
Ryan Houdek	b77a25b21a	Merge pull request #3818 from alyssarosenzweig/jit/shiftbymaskstozero ... JIT: fix ShiftFlags masking	2024-07-05 12:49:16 -07:00
Alyssa Rosenzweig	9db6931cea	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 10:49:12 -04:00
Ryan Houdek	bad5cef52b	unittests: Adds rotate with carry test for large rotates ... FEX-Emu currently doesn't do large rotates for small data sources correctly. This will fail CI until fixed in OpcodeDispatcher	2024-07-05 10:49:02 -04:00
Alyssa Rosenzweig	94bd79b2bf	OpcodeDispatcher: fix 8/16-bit RCR ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 10:49:02 -04:00
Alyssa Rosenzweig	b746146f4e	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 09:57:42 -04:00
Ryan Houdek	8ac9bb5c72	unittests: Adds test for flags when shifting by zero	2024-07-05 09:57:42 -04:00
Alyssa Rosenzweig	1b552a6f62	JIT: fix ShiftFlags masking ... we don't update flags for a nonzero shift that masks to zero. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-05 09:57:42 -04:00
Alyssa Rosenzweig	97329ccc7a	Merge pull request #3812 from Sonicadvance1/fix_rotates_with_zero ... OpcodeDispatcher: Fixes rotates with zero not zero extending 32-bit result	2024-07-05 09:48:01 -04:00
Mai	f2d1f2de56	Merge pull request #3817 from Sonicadvance1/fix_x87_integer_indefinite ... Softfloat: Fixes Integer indefinite return for 16-bit signed values	2024-07-04 23:11:44 -04:00
Ryan Houdek	692c2fae96	Merge pull request #3813 from alyssarosenzweig/bug/fix-sbb ... Fix 16-bit SBB	2024-07-04 19:52:37 -07:00
Mai	3d65b701a2	Merge pull request #3816 from Sonicadvance1/fix_long_signed_divide ... Arm64: Fixes long signed divide	2024-07-04 21:43:11 -04:00
Ryan Houdek	ecaca0fe15	unittests: Adds x87 integer indefinite test ... Tests 16-bit, 32-bit, and 64-bit integer conversions	2024-07-04 17:53:28 -07:00
Ryan Houdek	8955f83ef6	Softfloat: Fixes Integer indefinite return for 16-bit signed values ... Regardless of positive or negative value, if the converted integer doesn't fit in to the converted int16_t then it returns INT16_MIN.	2024-07-04 17:43:28 -07:00
Ryan Houdek	1a8aaebd79	unittests: Adds long signed divide test	2024-07-04 16:43:21 -07:00
Ryan Houdek	38a823cc54	Arm64: Fixes long signed divide ... The two halves are provided as two uint64_t values that shouldn't be sign extended between them. Treat them as uint64_t until combined in to a single int128_t. Fixes long signed divide.	2024-07-04 16:42:23 -07:00
Ryan Houdek	25306cb373	InstcountCI: Update	2024-07-04 14:35:43 -07:00
Ryan Houdek	1084a031e7	unittests: Adds test for previous fix ... All of these results would have failed except for the rorx result.	2024-07-04 14:35:43 -07:00
Ryan Houdek	f6ec99bede	OpcodeDispatcher: Fixes rotates with zero not zero extending 32-bit result ... For all the 32-bit rotates (except for RORX) we were failing to zero extend the 32-bit result to the destination register when the rotate was masked to zero. Ensure we do this.	2024-07-04 14:35:42 -07:00
Ryan Houdek	90a6647fa4	Merge pull request #3811 from alyssarosenzweig/ra/fix-lsp ... RA: fix interaction between SRA & shuffles	2024-07-04 14:20:46 -07:00
Alyssa Rosenzweig	a926bb81a9	InstCountCI: Update ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-04 16:58:45 -04:00
Alyssa Rosenzweig	fbf41e3149	unittests: add test for small sbc flags ... Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-04 16:58:45 -04:00
Alyssa Rosenzweig	a38205069b	OpcodeDispatcher: fix SBB carry flag ... do it the naive way, just applying the x86 definitions of SBB. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-04 16:58:45 -04:00
Alyssa Rosenzweig	2d75801024	unittests: add tricky RA test ... this fails on current main with blocksize=500 due to mentioned RA bug. passes with blocksize=1. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>	2024-07-04 13:37:13 -04:00