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633ea045e5
cmpxchg/cmpxchg8b doesn't have alignment requirements on x86, which means applications rely on unaligned behaviour support with it. Steam relies on this to work for a linked list array of jobs in some internal job queueing system. It will end up always aligning by offsets of 4 since it stores a couple of pointers. Doesn't currently support the case of unaligned cmpxchg8b crossing a cacheline, which ends up being semi-broken depending on which x86 behaviour the application is expected. Intel CPUs do the "Big ring lock" or "split locks". Which means accesses across cachelines are atomic. AMD CPUs will tear the value across the cacheline, which is expected x86 behaviour by spec. If they are expecting Intel behaviour, then that application is just broken on non-Intel platforms unless they are fine with a tear.