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0c7c7ba670
Most of these were relying on the upper 16bits of the 80bit MM registers to be zero. This isn't necessarily true as one will find out when running this under the host runner.
51 lines
996 B
NASM
51 lines
996 B
NASM
%ifdef CONFIG
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{
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"RegData": {
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"MM6": ["0x8000000000000000", "0x4000"],
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"MM7": ["0x8000000000000000", "0x3fff"]
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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mov rdx, 0xe0000000
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mov eax, 0x3f800000 ; 1.0
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mov [rdx + 8 * 0], eax
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mov eax, 0x40000000 ; 2.0
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mov [rdx + 8 * 1], eax
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mov eax, 0x40800000 ; 4.0
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mov [rdx + 8 * 2], eax
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fld dword [rdx + 8 * 0]
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o16 fstenv [rdx + 8 * 3]
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fld dword [rdx + 8 * 2]
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o16 fldenv [rdx + 8 * 3]
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; This will overwrite the previous load
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; This is since the control word is stored and reloaded
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fld dword [rdx + 8 * 1]
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; 14 bytes for 16bit
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; 2 Bytes : FCW
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; 2 Bytes : FSW
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; 2 bytes : FTW
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; 2 bytes : Instruction offset
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; 2 bytes : Instruction CS selector
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; 2 bytes : Data offset
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; 2 bytes : Data selector
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; 28 bytes for 32bit
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; 4 bytes : FCW
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; 4 bytes : FSW
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; 4 bytes : FTW
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; 4 bytes : Instruction pointer
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; 2 bytes : instruction pointer selector
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; 2 bytes : Opcode
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; 4 bytes : data pointer offset
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; 4 bytes : data pointer selector
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hlt
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