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3d23cd5765
In the event no source vectors alias the destination, we can just move the first source vector into it and then perform the divide without needing to move afterword.
53 lines
1.5 KiB
NASM
53 lines
1.5 KiB
NASM
%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM0": ["0x400000003F800000", "0x4080000040400000", "0x400000003F800000", "0x4080000040400000"],
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"XMM1": ["0x40C0000040A00000", "0x4100000040E00000", "0x40C0000040A00000", "0x4100000040E00000"],
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"XMM2": ["0x3EAAAAAB3E4CCCCD", "0x3F0000003EDB6DB7", "0x0000000000000000", "0x0000000000000000"],
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"XMM3": ["0x3EAAAAAB3E4CCCCD", "0x3F0000003EDB6DB7", "0x0000000000000000", "0x0000000000000000"],
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"XMM4": ["0x3EAAAAAB3E4CCCCD", "0x3F0000003EDB6DB7", "0x3EAAAAAB3E4CCCCD", "0x3F0000003EDB6DB7"],
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"XMM5": ["0x4040000040A00000", "0x4000000040155555", "0x4040000040A00000", "0x4000000040155555"],
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"XMM6": ["0x3EAAAAAB3E4CCCCD", "0x3F0000003EDB6DB7", "0x3EAAAAAB3E4CCCCD", "0x3F0000003EDB6DB7"],
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"XMM7": ["0x4040000040A00000", "0x4000000040155555", "0x4040000040A00000", "0x4000000040155555"]
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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lea rdx, [rel .data]
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vmovapd ymm0, [rdx]
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vmovapd ymm1, [rdx + 32]
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; Memory operand
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vdivps xmm2, xmm0, [rdx + 32]
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vdivps ymm4, ymm0, [rdx + 32]
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; Register only
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vdivps xmm3, xmm0, xmm1
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vdivps ymm5, ymm1, ymm0
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; Some tests for aliasing destination and source vectors
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vmovapd ymm6, ymm0
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vdivps ymm6, ymm6, ymm1
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vmovapd ymm7, ymm0
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vdivps ymm7, ymm1, ymm7
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hlt
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align 32
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.data:
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dq 0x400000003F800000 ; 2, 1
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dq 0x4080000040400000 ; 4, 3
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dq 0x400000003F800000 ; 2, 1
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dq 0x4080000040400000 ; 4, 3
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dq 0x40C0000040A00000 ; 6, 5
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dq 0x4100000040E00000 ; 8, 7
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dq 0x40C0000040A00000 ; 6, 5
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dq 0x4100000040E00000 ; 8, 7
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