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FEX/unittests/InstructionCountCI/VEX_map1.json
Alyssa Rosenzweig 598b99fe58 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-09-22 14:06:27 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"SVE128",
"SVE256"
],
"DisabledHostFeatures": [
"FCMA",
"RPRES",
"AFP",
"FLAGM",
"FLAGM2"
]
},
"Instructions": {
"vmovups xmm0, xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x10 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b"
]
},
"vmovups xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"SVE 128-bit load already zero's the upper bits",
"Map 1 0b00 0x10 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vmovups ymm0, ymm0": {
"ExpectedInstructionCount": 0,
"Comment": [
"Spurious moves",
"Map 1 0b00 0x10 256-bit"
],
"ExpectedArm64ASM": []
},
"vmovups ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x10 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vmovupd xmm0, xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x10 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b"
]
},
"vmovupd xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"SVE 128-bit load already zero's the upper bits",
"Map 1 0b01 0x10 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vmovupd ymm0, ymm0": {
"ExpectedInstructionCount": 0,
"Comment": [
"Spurious moves",
"Map 1 0b01 0x10 256-bit"
],
"ExpectedArm64ASM": []
},
"vmovupd ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x10 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vmovss xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"32-bit vector load already zero's the upper bits",
"Map 1 0b10 0x10 128-bit"
],
"ExpectedArm64ASM": [
"ldr s16, [x4]"
]
},
"vmovss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Insert in to first element could be more optimal, which is the common case.",
"Map 1 0b10 0x10 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[0], v18.s[0]"
]
},
"vmovsd xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"32-bit vector load already zero's the upper bits",
"Map 1 0b11 0x10 128-bit"
],
"ExpectedArm64ASM": [
"ldr d16, [x4]"
]
},
"vmovsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Insert in to first element could be more optimal, which is the common case.",
"Map 1 0b11 0x10 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[0], v18.d[0]"
]
},
"vmovups [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x11 128-bit"
],
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"vmovups [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x11 256-bit"
],
"ExpectedArm64ASM": [
"st1b {z16.b}, p7, [x4]"
]
},
"vmovupd [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x11 128-bit"
],
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"vmovupd [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x11 256-bit"
],
"ExpectedArm64ASM": [
"st1b {z16.b}, p7, [x4]"
]
},
"vmovss [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x11 128-bit"
],
"ExpectedArm64ASM": [
"str s16, [x4]"
]
},
"db 0xc5, 0xf2, 0x11, 0xc2": {
"ExpectedInstructionCount": 2,
"Comment": [
"vmovss xmm2, xmm1, xmm0",
"Need to manually encode since nasm won't encode this",
"Insert in to first element could be more optimal, which is the common case.",
"Map 1 0b10 0x11 128-bit"
],
"ExpectedArm64ASM": [
"mov v18.16b, v17.16b",
"mov v18.s[0], v16.s[0]"
]
},
"vmovsd [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b11 0x11 128-bit"
],
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"db 0xc5, 0xf3, 0x11, 0xc2": {
"ExpectedInstructionCount": 2,
"Comment": [
"vmovsd xmm2, xmm1, xmm0",
"Need to manually encode since nasm won't encode this",
"Insert in to first element could be more optimal, which is the common case.",
"Map 1 0b11 0x11 128-bit"
],
"ExpectedArm64ASM": [
"mov v18.16b, v17.16b",
"mov v18.d[0], v16.d[0]"
]
},
"vmovlps xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 3,
"Comment": [
"Insert in to first element could be more optimal, which is the common case.",
"Map 1 0b00 0x12 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"vmovlpd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 3,
"Comment": [
"Insert in to first element could be more optimal, which is the common case.",
"Map 1 0b01 0x12 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"vmovsldup xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x12 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"trn1 v16.4s, v2.4s, v2.4s"
]
},
"vmovsldup ymm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Could potentially be considered optimal.",
"Ideally the load happens directly in the destination register",
"This would lower memory pressure of this instruction by 1 temporary",
"But the more optimal implementation is still the same number of instructions",
"Map 1 0b10 0x12 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"trn1 z16.s, z2.s, z2.s"
]
},
"vmovddup xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x12 128-bit"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"dup v16.2d, v2.d[0]"
]
},
"vmovddup ymm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Could potentially be considered optimal.",
"Ideally the load happens directly in the destination register",
"This would lower memory pressure of this instruction by 1 temporary",
"But the more optimal implementation is still the same number of instructions",
"Map 1 0b11 0x12 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"trn1 z16.d, z2.d, z2.d"
]
},
"vmovlps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x13 128-bit"
],
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"vmovlpd [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x13 128-bit"
],
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"vunpcklps xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0x14 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"zip1 v16.4s, v17.4s, v2.4s"
]
},
"vunpcklps ymm0, ymm1, [rax]": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 1 0b00 0x14 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"zip1 z3.s, z17.s, z2.s",
"zip2 z2.s, z17.s, z2.s",
"mov z1.q, q2",
"mov z16.d, z3.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vunpcklpd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"zip1 v16.2d, v17.2d, v2.2d"
]
},
"vunpcklpd ymm0, ymm1, [rax]": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 1 0b01 0x14 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"zip1 z3.d, z17.d, z2.d",
"zip2 z2.d, z17.d, z2.d",
"mov z1.q, q2",
"mov z16.d, z3.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vunpckhps xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0x15 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"zip2 v16.4s, v17.4s, v2.4s"
]
},
"vunpckhps ymm0, ymm1, [rax]": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b00 0x15 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"zip1 z3.s, z17.s, z2.s",
"zip2 z2.s, z17.s, z2.s",
"mov z1.q, z3.q[1]",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vunpckhpd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"zip2 v16.2d, v17.2d, v2.2d"
]
},
"vunpckhpd ymm0, ymm1, [rax]": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x15 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"zip1 z3.d, z17.d, z2.d",
"zip2 z2.d, z17.d, z2.d",
"mov z1.q, z3.q[1]",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vmovhps xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.8b, v17.8b",
"ldr d3, [x4]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v3.d[0]"
]
},
"vmovhpd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.8b, v17.8b",
"ldr d3, [x4]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v3.d[0]"
]
},
"vmovlhps xmm0, xmm1, xmm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.8b, v17.8b",
"mov v3.8b, v17.8b",
"mov v16.16b, v2.16b",
"mov v16.d[1], v3.d[0]"
]
},
"vmovshdup xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x16 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"trn2 v16.4s, v2.4s, v2.4s"
]
},
"vmovshdup ymm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x16 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"trn2 z16.s, z2.s, z2.s"
]
},
"vmovhps [rax], xmm0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0x17 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.d[0], v16.d[1]",
"str d2, [x4]"
]
},
"vmovhpd [rax], xmm0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0x17 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.d[0], v16.d[1]",
"str d2, [x4]"
]
},
"vmovmskps rax, xmm0": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0x50 128-bit"
],
"ExpectedArm64ASM": [
"ushr v2.4s, v16.4s, #31",
"index z3.s, #0, #1",
"ushl v2.4s, v2.4s, v3.4s",
"addv s2, v2.4s",
"mov w4, v2.s[0]"
]
},
"vmovmskps rax, ymm0": {
"ExpectedInstructionCount": 41,
"Comment": [
"Map 1 0b00 0x50 256-bit"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, v16.s[0]",
"lsr w21, w21, #31",
"orr x20, x20, x21",
"mov w21, v16.s[1]",
"lsr w21, w21, #31",
"lsl w21, w21, #1",
"orr x20, x20, x21",
"mov w21, v16.s[2]",
"lsr w21, w21, #31",
"lsl w21, w21, #2",
"orr x20, x20, x21",
"mov w21, v16.s[3]",
"lsr w21, w21, #31",
"lsl w21, w21, #3",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[0]",
"lsr w21, w21, #31",
"lsl w21, w21, #4",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[1]",
"lsr w21, w21, #31",
"lsl w21, w21, #5",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[2]",
"lsr w21, w21, #31",
"lsl w21, w21, #6",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[3]",
"lsr w21, w21, #31",
"lsl w21, w21, #7",
"orr x20, x20, x21",
"mov w4, w20"
]
},
"vmovmskpd rax, xmm0": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x50 128-bit"
],
"ExpectedArm64ASM": [
"uzp2 v2.4s, v16.4s, v16.4s",
"mov x20, v2.d[0]",
"bfi x20, x20, #31, #32",
"lsr x4, x20, #62"
]
},
"vmovmskpd rax, ymm0": {
"ExpectedInstructionCount": 21,
"Comment": [
"Map 1 0b01 0x50 256-bit"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov x21, v16.d[0]",
"lsr x21, x21, #63",
"orr x20, x20, x21",
"mov x21, v16.d[1]",
"lsr x21, x21, #63",
"lsl x21, x21, #1",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov x21, v16.d[0]",
"lsr x21, x21, #63",
"lsl x21, x21, #2",
"orr x20, x20, x21",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov x21, v16.d[1]",
"lsr x21, x21, #63",
"lsl x21, x21, #3",
"orr x20, x20, x21",
"mov w4, w20"
]
},
"vsqrtps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x51 128-bit"
],
"ExpectedArm64ASM": [
"fsqrt v16.4s, v17.4s"
]
},
"vsqrtps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x51 256-bit"
],
"ExpectedArm64ASM": [
"fsqrt z16.s, p7/m, z17.s"
]
},
"vsqrtpd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x51 128-bit"
],
"ExpectedArm64ASM": [
"fsqrt v16.2d, v17.2d"
]
},
"vsqrtpd ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x51 256-bit"
],
"ExpectedArm64ASM": [
"fsqrt z16.d, p7/m, z17.d"
]
},
"vsqrtss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x51 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fsqrt s0, s18",
"mov v16.s[0], v0.s[0]"
]
},
"vsqrtsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x51 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fsqrt d0, d18",
"mov v16.d[0], v0.d[0]"
]
},
"vrsqrtps xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0x52 128-bit"
],
"ExpectedArm64ASM": [
"fmov v0.4s, #0x70 (1.0000)",
"fsqrt v1.4s, v17.4s",
"fdiv v16.4s, v0.4s, v1.4s"
]
},
"vrsqrtps ymm0, ymm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0x52 256-bit"
],
"ExpectedArm64ASM": [
"fsqrt z0.s, p7/m, z17.s",
"fmov z16.s, #0x70 (1.0000)",
"fdiv z16.s, p7/m, z16.s, z0.s"
]
},
"vrsqrtss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b10 0x52 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fmov s0, #0x70 (1.0000)",
"fsqrt s1, s18",
"fdiv s0, s0, s1",
"mov v16.s[0], v0.s[0]"
]
},
"vrcpps xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0x53 128-bit"
],
"ExpectedArm64ASM": [
"fmov v0.4s, #0x70 (1.0000)",
"fdiv v16.4s, v0.4s, v17.4s"
]
},
"vrcpps ymm0, ymm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0x53 256-bit"
],
"ExpectedArm64ASM": [
"fmov z0.s, #0x70 (1.0000)",
"fdiv z0.s, p7/m, z0.s, z17.s",
"mov z16.d, z0.d"
]
},
"vrcpss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b10 0x53 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fmov s0, #0x70 (1.0000)",
"fdiv s0, s0, s18",
"mov v16.s[0], v0.s[0]"
]
},
"vandps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x54 128-bit"
],
"ExpectedArm64ASM": [
"and v16.16b, v16.16b, v17.16b"
]
},
"vandps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x54 256-bit"
],
"ExpectedArm64ASM": [
"and z16.d, z16.d, z17.d"
]
},
"vandpd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x54 128-bit"
],
"ExpectedArm64ASM": [
"and v16.16b, v16.16b, v17.16b"
]
},
"vandpd ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x54 256-bit"
],
"ExpectedArm64ASM": [
"and z16.d, z16.d, z17.d"
]
},
"vandnps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x55 128-bit"
],
"ExpectedArm64ASM": [
"bic v16.16b, v17.16b, v16.16b"
]
},
"vandnps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x55 256-bit"
],
"ExpectedArm64ASM": [
"bic z16.d, z17.d, z16.d"
]
},
"vandnpd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x55 128-bit"
],
"ExpectedArm64ASM": [
"bic v16.16b, v17.16b, v16.16b"
]
},
"vandnpd ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x55 256-bit"
],
"ExpectedArm64ASM": [
"bic z16.d, z17.d, z16.d"
]
},
"vorps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x56 128-bit"
],
"ExpectedArm64ASM": [
"orr v16.16b, v16.16b, v17.16b"
]
},
"vorps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x56 256-bit"
],
"ExpectedArm64ASM": [
"orr z16.d, z16.d, z17.d"
]
},
"vorpd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x56 128-bit"
],
"ExpectedArm64ASM": [
"orr v16.16b, v16.16b, v17.16b"
]
},
"vorpd ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x56 256-bit"
],
"ExpectedArm64ASM": [
"orr z16.d, z16.d, z17.d"
]
},
"vxorps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x57 128-bit"
],
"ExpectedArm64ASM": [
"eor v16.16b, v16.16b, v17.16b"
]
},
"vxorps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x57 256-bit"
],
"ExpectedArm64ASM": [
"eor z16.d, z16.d, z17.d"
]
},
"vxorpd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x57 128-bit"
],
"ExpectedArm64ASM": [
"eor v16.16b, v16.16b, v17.16b"
]
},
"vxorpd ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x57 256-bit"
],
"ExpectedArm64ASM": [
"eor z16.d, z16.d, z17.d"
]
},
"vxorps xmm0, xmm1, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"xor with itself to get zero register",
"Map 1 0b00 0x57 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vxorps ymm0, ymm1, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"xor with itself to get zero register",
"Map 1 0b00 0x57 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vxorpd xmm0, xmm1, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"xor with itself to get zero register",
"Map 1 0b01 0x57 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vxorpd ymm0, ymm1, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"xor with itself to get zero register",
"Map 1 0b01 0x57 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vpunpcklbw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x60 128-bit"
],
"ExpectedArm64ASM": [
"zip1 v16.16b, v17.16b, v18.16b"
]
},
"vpunpcklbw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x60 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.b, z17.b, z18.b",
"zip2 z3.b, z17.b, z18.b",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpunpcklwd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x61 128-bit"
],
"ExpectedArm64ASM": [
"zip1 v16.8h, v17.8h, v18.8h"
]
},
"vpunpcklwd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x61 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.h, z17.h, z18.h",
"zip2 z3.h, z17.h, z18.h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpunpckldq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x62 128-bit"
],
"ExpectedArm64ASM": [
"zip1 v16.4s, v17.4s, v18.4s"
]
},
"vpunpckldq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x62 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.s, z17.s, z18.s",
"zip2 z3.s, z17.s, z18.s",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpacksswb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x63 128-bit"
],
"ExpectedArm64ASM": [
"sqxtn v16.8b, v17.8h",
"sqxtn2 v16.16b, v18.8h"
]
},
"vpacksswb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 19,
"Comment": [
"Map 1 0b01 0x63 256-bit"
],
"ExpectedArm64ASM": [
"sqxtnb z1.b, z18.h",
"uzp1 z1.b, z1.b, z1.b",
"sqxtnb z2.b, z17.h",
"uzp1 z2.b, z2.b, z2.b",
"splice z2.b, p6, z2.b, z1.b",
"mov z1.d, z2.d[1]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[2]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpcmpgtb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x64 128-bit"
],
"ExpectedArm64ASM": [
"cmgt v16.16b, v17.16b, v18.16b"
]
},
"vpcmpgtb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x64 256-bit"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"cmpgt p0.b, p7/z, z17.b, z18.b",
"not z0.b, p0/m, z17.b",
"movprfx z16.b, p0/z, z17.b",
"orr z16.b, p0/m, z16.b, z0.b",
"msr nzcv, x0"
]
},
"vpcmpgtw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x65 128-bit"
],
"ExpectedArm64ASM": [
"cmgt v16.8h, v17.8h, v18.8h"
]
},
"vpcmpgtw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x65 256-bit"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"cmpgt p0.h, p7/z, z17.h, z18.h",
"not z0.h, p0/m, z17.h",
"movprfx z16.h, p0/z, z17.h",
"orr z16.h, p0/m, z16.h, z0.h",
"msr nzcv, x0"
]
},
"vpcmpgtd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x66 128-bit"
],
"ExpectedArm64ASM": [
"cmgt v16.4s, v17.4s, v18.4s"
]
},
"vpcmpgtd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x66 256-bit"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"cmpgt p0.s, p7/z, z17.s, z18.s",
"not z0.s, p0/m, z17.s",
"movprfx z16.s, p0/z, z17.s",
"orr z16.s, p0/m, z16.s, z0.s",
"msr nzcv, x0"
]
},
"vpackuswb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x67 128-bit"
],
"ExpectedArm64ASM": [
"sqxtun v16.8b, v17.8h",
"sqxtun2 v16.16b, v18.8h"
]
},
"vpackuswb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 19,
"Comment": [
"Map 1 0b01 0x67 256-bit"
],
"ExpectedArm64ASM": [
"sqxtunb z1.b, z18.h",
"uzp1 z1.b, z1.b, z1.b",
"sqxtunb z2.b, z17.h",
"uzp1 z2.b, z2.b, z2.b",
"splice z2.b, p6, z2.b, z1.b",
"mov z1.d, z2.d[1]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[2]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpshufd xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v17.s[0]",
"mov v2.s[2], v17.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[0]"
]
},
"vpshufd xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.s[0], v17.s[1]",
"mov v2.s[1], v17.s[0]",
"mov v2.s[2], v17.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[0]"
]
},
"vpshufd xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.s[0], v17.s[2]",
"mov v2.s[1], v17.s[0]",
"mov v2.s[2], v17.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[0]"
]
},
"vpshufd xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.s[0], v17.s[3]",
"mov v2.s[1], v17.s[0]",
"mov v2.s[2], v17.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[0]"
]
},
"vpshufd ymm0, ymm1, 00b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b01 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, s17",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpshufd ymm0, ymm1, 01b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b01 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, z17.s[1]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpshufd ymm0, ymm1, 10b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b01 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, z17.s[2]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpshufd ymm0, ymm1, 11b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b01 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, z17.s[3]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpshufhw xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[4], v17.h[4]",
"mov v2.h[5], v17.h[4]",
"mov v2.h[6], v17.h[4]",
"mov v16.16b, v2.16b",
"mov v16.h[7], v17.h[4]"
]
},
"vpshufhw xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[4], v17.h[5]",
"mov v2.h[5], v17.h[4]",
"mov v2.h[6], v17.h[4]",
"mov v16.16b, v2.16b",
"mov v16.h[7], v17.h[4]"
]
},
"vpshufhw xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[4], v17.h[6]",
"mov v2.h[5], v17.h[4]",
"mov v2.h[6], v17.h[4]",
"mov v16.16b, v2.16b",
"mov v16.h[7], v17.h[4]"
]
},
"vpshufhw xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[4], v17.h[7]",
"mov v2.h[5], v17.h[4]",
"mov v2.h[6], v17.h[4]",
"mov v16.16b, v2.16b",
"mov v16.h[7], v17.h[4]"
]
},
"vpshufhw ymm0, ymm1, 00b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b10 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[4]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-3",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #7",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshufhw ymm0, ymm1, 01b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b10 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[5]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[13]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-3",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #7",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshufhw ymm0, ymm1, 10b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b10 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[6]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[14]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-3",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #7",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshufhw ymm0, ymm1, 11b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b10 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[7]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[15]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-3",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #7",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshuflw xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[0], v17.h[0]",
"mov v2.h[1], v17.h[0]",
"mov v2.h[2], v17.h[0]",
"mov v16.16b, v2.16b",
"mov v16.h[3], v17.h[0]"
]
},
"vpshuflw xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[0], v17.h[1]",
"mov v2.h[1], v17.h[0]",
"mov v2.h[2], v17.h[0]",
"mov v16.16b, v2.16b",
"mov v16.h[3], v17.h[0]"
]
},
"vpshuflw xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[0], v17.h[2]",
"mov v2.h[1], v17.h[0]",
"mov v2.h[2], v17.h[0]",
"mov v16.16b, v2.16b",
"mov v16.h[3], v17.h[0]"
]
},
"vpshuflw xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0x70 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v17.16b",
"mov v2.h[0], v17.h[3]",
"mov v2.h[1], v17.h[0]",
"mov v2.h[2], v17.h[0]",
"mov v16.16b, v2.16b",
"mov v16.h[3], v17.h[0]"
]
},
"vpshuflw ymm0, ymm1, 00b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b11 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, h17",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-8",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #0",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-7",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #3",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshuflw ymm0, ymm1, 01b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b11 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[1]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-8",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[9]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #0",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-7",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #3",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshuflw ymm0, ymm1, 10b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b11 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[2]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-8",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[10]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #0",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-7",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #3",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpshuflw ymm0, ymm1, 11b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b11 0x70 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.h, z17.h[3]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-8",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[11]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #0",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-7",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, h17",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[8]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #3",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpcmpeqb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x74 128-bit"
],
"ExpectedArm64ASM": [
"cmeq v16.16b, v17.16b, v18.16b"
]
},
"vpcmpeqb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x74 256-bit"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"cmpeq p0.b, p7/z, z17.b, z18.b",
"not z0.b, p0/m, z17.b",
"movprfx z16.b, p0/z, z17.b",
"orr z16.b, p0/m, z16.b, z0.b",
"msr nzcv, x0"
]
},
"vpcmpeqw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x75 128-bit"
],
"ExpectedArm64ASM": [
"cmeq v16.8h, v17.8h, v18.8h"
]
},
"vpcmpeqw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x75 256-bit"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"cmpeq p0.h, p7/z, z17.h, z18.h",
"not z0.h, p0/m, z17.h",
"movprfx z16.h, p0/z, z17.h",
"orr z16.h, p0/m, z16.h, z0.h",
"msr nzcv, x0"
]
},
"vpcmpeqd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x76 128-bit"
],
"ExpectedArm64ASM": [
"cmeq v16.4s, v17.4s, v18.4s"
]
},
"vpcmpeqd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x76 256-bit"
],
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"cmpeq p0.s, p7/z, z17.s, z18.s",
"not z0.s, p0/m, z17.s",
"movprfx z16.s, p0/z, z17.s",
"orr z16.s, p0/m, z16.s, z0.s",
"msr nzcv, x0"
]
},
"vzeroupper": {
"ExpectedInstructionCount": 16,
"Comment": [
"Might need to revisit this if move renaming ends up slower than some other clearing",
"Map 1 0b01 0x77 L=0"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"mov v17.16b, v17.16b",
"mov v18.16b, v18.16b",
"mov v19.16b, v19.16b",
"mov v20.16b, v20.16b",
"mov v21.16b, v21.16b",
"mov v22.16b, v22.16b",
"mov v23.16b, v23.16b",
"mov v24.16b, v24.16b",
"mov v25.16b, v25.16b",
"mov v26.16b, v26.16b",
"mov v27.16b, v27.16b",
"mov v28.16b, v28.16b",
"mov v29.16b, v29.16b",
"mov v30.16b, v30.16b",
"mov v31.16b, v31.16b"
]
},
"vzeroall": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 1 0b01 0x77 L=1"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0",
"movi v17.2d, #0x0",
"movi v18.2d, #0x0",
"movi v19.2d, #0x0",
"movi v20.2d, #0x0",
"movi v21.2d, #0x0",
"movi v22.2d, #0x0",
"movi v23.2d, #0x0",
"movi v24.2d, #0x0",
"movi v25.2d, #0x0",
"movi v26.2d, #0x0",
"movi v27.2d, #0x0",
"movi v28.2d, #0x0",
"movi v29.2d, #0x0",
"movi v30.2d, #0x0",
"movi v31.2d, #0x0"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x00": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmeq v16.4s, v17.4s, v18.4s"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x00": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmeq p0.s, p7/z, z17.s, z18.s",
"not z0.s, p0/m, z17.s",
"movprfx z16.s, p0/z, z17.s",
"orr z16.s, p0/m, z16.s, z0.s"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x01": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v16.4s, v18.4s, v17.4s"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x01": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.s, p7/z, z18.s, z17.s",
"not z0.s, p0/m, z18.s",
"movprfx z16.s, p0/z, z18.s",
"orr z16.s, p0/m, z16.s, z0.s"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x02": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v16.4s, v18.4s, v17.4s"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x02": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmge p0.s, p7/z, z18.s, z17.s",
"not z0.s, p0/m, z18.s",
"movprfx z16.s, p0/z, z18.s",
"orr z16.s, p0/m, z16.s, z0.s"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x03": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v0.4s, v17.4s, v18.4s",
"fcmgt v1.4s, v18.4s, v17.4s",
"orr v16.16b, v0.16b, v1.16b",
"mvn v16.16b, v16.16b"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x03": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmuo p0.s, p7/z, z17.s, z18.s",
"not z0.s, p0/m, z17.s",
"movprfx z16.s, p0/z, z17.s",
"orr z16.s, p0/m, z16.s, z0.s"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x04": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmeq v16.4s, v17.4s, v18.4s",
"mvn v16.16b, v16.16b"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x04": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmne p0.s, p7/z, z17.s, z18.s",
"not z0.s, p0/m, z17.s",
"movprfx z16.s, p0/z, z17.s",
"orr z16.s, p0/m, z16.s, z0.s"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x05": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v2.4s, v18.4s, v17.4s",
"mvn v16.16b, v2.16b"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x05": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.s, p7/z, z18.s, z17.s",
"not z0.s, p0/m, z18.s",
"movprfx z2.s, p0/z, z18.s",
"orr z2.s, p0/m, z2.s, z0.s",
"not z16.b, p7/m, z2.b"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x06": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v2.4s, v18.4s, v17.4s",
"mvn v16.16b, v2.16b"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x06": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmge p0.s, p7/z, z18.s, z17.s",
"not z0.s, p0/m, z18.s",
"movprfx z2.s, p0/z, z18.s",
"orr z2.s, p0/m, z2.s, z0.s",
"not z16.b, p7/m, z2.b"
]
},
"vcmpps xmm0, xmm1, xmm2, 0x07": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v0.4s, v17.4s, v18.4s",
"fcmgt v1.4s, v18.4s, v17.4s",
"orr v16.16b, v0.16b, v1.16b"
]
},
"vcmpps ymm0, ymm1, ymm2, 0x07": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmuo p0.s, p7/z, z17.s, z18.s",
"not p0.b, p7/z, p0.b",
"not z0.s, p0/m, z17.s",
"movprfx z16.s, p0/z, z17.s",
"orr z16.s, p0/m, z16.s, z0.s"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x00": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmeq v16.2d, v17.2d, v18.2d"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x00": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmeq p0.d, p7/z, z17.d, z18.d",
"not z0.d, p0/m, z17.d",
"movprfx z16.d, p0/z, z17.d",
"orr z16.d, p0/m, z16.d, z0.d"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x01": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v16.2d, v18.2d, v17.2d"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x01": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.d, p7/z, z18.d, z17.d",
"not z0.d, p0/m, z18.d",
"movprfx z16.d, p0/z, z18.d",
"orr z16.d, p0/m, z16.d, z0.d"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x02": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v16.2d, v18.2d, v17.2d"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x02": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmge p0.d, p7/z, z18.d, z17.d",
"not z0.d, p0/m, z18.d",
"movprfx z16.d, p0/z, z18.d",
"orr z16.d, p0/m, z16.d, z0.d"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x03": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v0.2d, v17.2d, v18.2d",
"fcmgt v1.2d, v18.2d, v17.2d",
"orr v16.16b, v0.16b, v1.16b",
"mvn v16.16b, v16.16b"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x03": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmuo p0.d, p7/z, z17.d, z18.d",
"not z0.d, p0/m, z17.d",
"movprfx z16.d, p0/z, z17.d",
"orr z16.d, p0/m, z16.d, z0.d"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x04": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmeq v16.2d, v17.2d, v18.2d",
"mvn v16.16b, v16.16b"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x04": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmne p0.d, p7/z, z17.d, z18.d",
"not z0.d, p0/m, z17.d",
"movprfx z16.d, p0/z, z17.d",
"orr z16.d, p0/m, z16.d, z0.d"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x05": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v2.2d, v18.2d, v17.2d",
"mvn v16.16b, v2.16b"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x05": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.d, p7/z, z18.d, z17.d",
"not z0.d, p0/m, z18.d",
"movprfx z2.d, p0/z, z18.d",
"orr z2.d, p0/m, z2.d, z0.d",
"not z16.b, p7/m, z2.b"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x06": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v2.2d, v18.2d, v17.2d",
"mvn v16.16b, v2.16b"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x06": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmge p0.d, p7/z, z18.d, z17.d",
"not z0.d, p0/m, z18.d",
"movprfx z2.d, p0/z, z18.d",
"orr z2.d, p0/m, z2.d, z0.d",
"not z16.b, p7/m, z2.b"
]
},
"vcmppd xmm0, xmm1, xmm2, 0x07": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge v0.2d, v17.2d, v18.2d",
"fcmgt v1.2d, v18.2d, v17.2d",
"orr v16.16b, v0.16b, v1.16b"
]
},
"vcmppd ymm0, ymm1, ymm2, 0x07": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0xC2 256-bit"
],
"ExpectedArm64ASM": [
"fcmuo p0.d, p7/z, z17.d, z18.d",
"not p0.b, p7/z, p0.b",
"not z0.d, p0/m, z17.d",
"movprfx z16.d, p0/z, z17.d",
"orr z16.d, p0/m, z16.d, z0.d"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x00": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq s0, s18, s17",
"mov v16.s[0], v0.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x01": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmgt s0, s18, s17",
"mov v16.s[0], v0.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x02": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmge s0, s18, s17",
"mov v16.s[0], v0.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x03": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmge s0, s17, s18",
"fcmgt s1, s18, s17",
"orr v0.8b, v0.8b, v1.8b",
"mvn v0.8b, v0.8b",
"mov v16.s[0], v0.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x04": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq s0, s18, s17",
"mvn v0.8b, v0.8b",
"mov v16.s[0], v0.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x05": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt s2, s18, s17",
"mvn v2.16b, v2.16b",
"mov v16.16b, v17.16b",
"mov v16.s[0], v2.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x06": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge s2, s18, s17",
"mvn v2.16b, v2.16b",
"mov v16.16b, v17.16b",
"mov v16.s[0], v2.s[0]"
]
},
"vcmpss xmm0, xmm1, xmm2, 0x07": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b10 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmge s0, s17, s18",
"fcmgt s1, s18, s17",
"orr v0.8b, v0.8b, v1.8b",
"mov v16.s[0], v0.s[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x00": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq d0, d18, d17",
"mov v16.d[0], v0.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x01": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmgt d0, d18, d17",
"mov v16.d[0], v0.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x02": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmge d0, d18, d17",
"mov v16.d[0], v0.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x03": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmge d0, d17, d18",
"fcmgt d1, d18, d17",
"orr v0.8b, v0.8b, v1.8b",
"mvn v0.8b, v0.8b",
"mov v16.d[0], v0.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x04": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmeq d0, d18, d17",
"mvn v0.8b, v0.8b",
"mov v16.d[0], v0.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x05": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt d2, d18, d17",
"mvn v2.16b, v2.16b",
"mov v16.16b, v17.16b",
"mov v16.d[0], v2.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x06": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"fcmge d2, d18, d17",
"mvn v2.16b, v2.16b",
"mov v16.16b, v17.16b",
"mov v16.d[0], v2.d[0]"
]
},
"vcmpsd xmm0, xmm1, xmm2, 0x07": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b11 0xC2 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcmge d0, d17, d18",
"fcmgt d1, d18, d17",
"orr v0.8b, v0.8b, v1.8b",
"mov v16.d[0], v0.d[0]"
]
},
"vpinsrw xmm0, xmm0, eax, 000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.h[0], w4",
"mov v16.16b, v2.16b"
]
},
"vpinsrw xmm0, xmm1, eax, 000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.h[0], w4"
]
},
"vpinsrw xmm0, xmm1, eax, 001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.h[1], w4"
]
},
"vpinsrw xmm0, xmm1, eax, 111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.h[7], w4"
]
},
"vpextrw eax, xmm0, 000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC5 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[0]"
]
},
"vpextrw eax, xmm0, 001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC5 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[1]"
]
},
"vpextrw eax, xmm0, 111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC5 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[7]"
]
},
"vpextrw [rax], xmm0, 000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC5 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[0], [x4]"
]
},
"vpextrw [rax], xmm0, 001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC5 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[1], [x4]"
]
},
"vpextrw [rax], xmm0, 111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC5 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[7], [x4]"
]
},
"vshufps xmm0, xmm1, xmm2, 00b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[0]",
"dup v3.4s, v18.s[0]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"vshufps ymm0, ymm1, ymm2, 00b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b00 0xC6 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, s17",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vshufps xmm0, xmm1, xmm2, 01b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2000]",
"ldr q2, [x0, #16]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
},
"vshufps ymm0, ymm1, ymm2, 01b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b00 0xC6 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, z17.s[1]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vshufps xmm0, xmm1, xmm2, 10b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2000]",
"ldr q2, [x0, #32]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
},
"vshufps ymm0, ymm1, ymm2, 10b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b00 0xC6 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, z17.s[2]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vshufps xmm0, xmm1, xmm2, 11b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #2000]",
"ldr q2, [x0, #48]",
"tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
]
},
"vshufps ymm0, ymm1, ymm2, 11b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 1 0b00 0xC6 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.s, z17.s[3]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vshufpd xmm0, xmm1, xmm2, 0b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"zip1 v16.2d, v17.2d, v18.2d"
]
},
"vshufpd ymm0, ymm1, ymm2, 0b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 1 0b01 0xC6 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.d, d17",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vshufpd xmm0, xmm1, xmm2, 1b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xC6 128-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v17.16b, v18.16b, #8"
]
},
"vshufpd ymm0, ymm1, ymm2, 1b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 1 0b01 0xC6 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.d, z17.d[1]",
"mov z2.d, z17.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vmovaps xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x28 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vmovaps ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x28 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vmovaps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x29 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vmovaps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x29 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z17.d"
]
},
"vmovapd xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x28 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vmovapd ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x28 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vmovapd xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x29 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vmovapd ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x29 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z17.d"
]
},
"vmovaps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x29 128-bit"
],
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"vmovaps [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x29 256-bit"
],
"ExpectedArm64ASM": [
"st1b {z16.b}, p7, [x4]"
]
},
"vmovapd [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x29 128-bit"
],
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"vmovapd [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x29 256-bit"
],
"ExpectedArm64ASM": [
"st1b {z16.b}, p7, [x4]"
]
},
"vcvtsi2ss xmm0, xmm1, eax": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x2A 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"scvtf s0, w4",
"mov v16.s[0], v0.s[0]"
]
},
"vcvtsi2ss xmm0, xmm1, rax": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x2A 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"scvtf s0, x4",
"mov v16.s[0], v0.s[0]"
]
},
"vcvtsi2sd xmm0, xmm1, eax": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x2A 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"scvtf d0, w4",
"mov v16.d[0], v0.d[0]"
]
},
"vcvtsi2sd xmm0, xmm1, rax": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x2A 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"scvtf d0, x4",
"mov v16.d[0], v0.d[0]"
]
},
"vmovntps [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x2B 128-bit"
],
"ExpectedArm64ASM": [
"stnt1b {z16.b}, p6, [x4]"
]
},
"vmovntps [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x2B 256-bit"
],
"ExpectedArm64ASM": [
"stnt1b {z16.b}, p7, [x4]"
]
},
"vmovntpd [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x2B 128-bit"
],
"ExpectedArm64ASM": [
"stnt1b {z16.b}, p6, [x4]"
]
},
"vmovntpd [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x2B 256-bit"
],
"ExpectedArm64ASM": [
"stnt1b {z16.b}, p7, [x4]"
]
},
"vcvttss2si eax, xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs w4, s16"
]
},
"vcvttss2si rax, xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs x4, s16"
]
},
"vcvttsd2si eax, xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b11 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs w4, d16"
]
},
"vcvttsd2si rax, xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b11 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs x4, d16"
]
},
"vcvtss2si eax, xmm0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti s0, s16",
"fcvtzs w4, s0"
]
},
"vcvtss2si rax, xmm0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti s0, s16",
"fcvtzs x4, s0"
]
},
"vcvtsd2si eax, xmm0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti d0, d16",
"fcvtzs x4, d0"
]
},
"vcvtsd2si rax, xmm0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b11 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"frinti d0, d16",
"fcvtzs x4, d0"
]
},
"vucomiss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vucomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vcomiss xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"fcmp s16, s17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vcomisd xmm0, xmm1": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"fcmp d16, d17",
"mov w27, #0x0",
"cset w26, vc",
"csetm x0, eq",
"ccmn x26, x0, #nzCv, le"
]
},
"vaddps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x58 128-bit"
],
"ExpectedArm64ASM": [
"fadd v16.4s, v17.4s, v18.4s"
]
},
"vaddps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x58 256-bit"
],
"ExpectedArm64ASM": [
"fadd z16.s, z17.s, z18.s"
]
},
"vaddpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x58 128-bit"
],
"ExpectedArm64ASM": [
"fadd v16.2d, v17.2d, v18.2d"
]
},
"vaddpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x58 256-bit"
],
"ExpectedArm64ASM": [
"fadd z16.d, z17.d, z18.d"
]
},
"vaddss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x58 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fadd s0, s17, s18",
"mov v16.s[0], v0.s[0]"
]
},
"vaddsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x58 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fadd d0, d17, d18",
"mov v16.d[0], v0.d[0]"
]
},
"vmulps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x59 128-bit"
],
"ExpectedArm64ASM": [
"fmul v16.4s, v17.4s, v18.4s"
]
},
"vmulps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x59 256-bit"
],
"ExpectedArm64ASM": [
"fmul z16.s, z17.s, z18.s"
]
},
"vmulpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x59 128-bit"
],
"ExpectedArm64ASM": [
"fmul v16.2d, v17.2d, v18.2d"
]
},
"vmulpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x59 256-bit"
],
"ExpectedArm64ASM": [
"fmul z16.d, z17.d, z18.d"
]
},
"vmulss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x59 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fmul s0, s17, s18",
"mov v16.s[0], v0.s[0]"
]
},
"vmulsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x59 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fmul d0, d17, d18",
"mov v16.d[0], v0.d[0]"
]
},
"vcvtps2pd xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0x5a 128-bit"
],
"ExpectedArm64ASM": [
"fcvtl v2.2d, v17.2s",
"mov v16.16b, v2.16b"
]
},
"vcvtpd2ps xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x5a 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x4]",
"fcvtn v16.2s, v2.2d"
]
},
"vcvtpd2ps xmm0, yword [rax]": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x5a 128-bit"
],
"ExpectedArm64ASM": [
"ld1b {z2.b}, p7/z, [x4]",
"fcvtnt z2.s, p7/m, z2.d",
"uzp2 z2.s, z2.s, z2.s",
"mov v16.16b, v2.16b"
]
},
"vcvtpd2ps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x5a 128-bit"
],
"ExpectedArm64ASM": [
"fcvtn v16.2s, v17.2d"
]
},
"vcvtss2sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x5a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcvt d0, s18",
"mov v16.d[0], v0.d[0]"
]
},
"vcvtsd2ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x5a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fcvt s0, d18",
"mov v16.s[0], v0.s[0]"
]
},
"vcvtdq2ps xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"scvtf v16.4s, v17.4s"
]
},
"vcvtdq2ps ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"scvtf z16.s, p7/m, z17.s"
]
},
"vcvtps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"frinti v16.4s, v17.4s",
"fcvtzs v16.4s, v16.4s"
]
},
"vcvtps2dq ymm0, ymm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"frinti z16.s, p7/m, z17.s",
"fcvtzs z16.s, p7/m, z16.s"
]
},
"vcvttps2dq xmm0, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x5b 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs v16.4s, v17.4s"
]
},
"vcvttps2dq ymm0, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x5b 256-bit"
],
"ExpectedArm64ASM": [
"fcvtzs z16.s, p7/m, z17.s"
]
},
"vsubps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x5c 128-bit"
],
"ExpectedArm64ASM": [
"fsub v16.4s, v17.4s, v18.4s"
]
},
"vsubps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x5c 256-bit"
],
"ExpectedArm64ASM": [
"fsub z16.s, z17.s, z18.s"
]
},
"vsubpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x5c 128-bit"
],
"ExpectedArm64ASM": [
"fsub v16.2d, v17.2d, v18.2d"
]
},
"vsubpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x5c 256-bit"
],
"ExpectedArm64ASM": [
"fsub z16.d, z17.d, z18.d"
]
},
"vsubss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x5c 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fsub s0, s17, s18",
"mov v16.s[0], v0.s[0]"
]
},
"vsubsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x5c 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fsub d0, d17, d18",
"mov v16.d[0], v0.d[0]"
]
},
"vminps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0x5d 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v0.4s, v18.4s, v17.4s",
"mov v16.16b, v17.16b",
"bif v16.16b, v18.16b, v0.16b"
]
},
"vminps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b00 0x5d 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.s, p7/z, z18.s, z17.s",
"not p0.b, p7/z, p0.b",
"mov z0.d, z17.d",
"mov z0.s, p0/m, z18.s",
"mov z16.d, z0.d"
]
},
"vminpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0x5d 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v0.2d, v18.2d, v17.2d",
"mov v16.16b, v17.16b",
"bif v16.16b, v18.16b, v0.16b"
]
},
"vminpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x5d 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.d, p7/z, z18.d, z17.d",
"not p0.b, p7/z, p0.b",
"mov z0.d, z17.d",
"mov z0.d, p0/m, z18.d",
"mov z16.d, z0.d"
]
},
"vminss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x5d 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"mov v16.16b, v17.16b",
"fcmp s17, s18",
"fcsel s0, s17, s18, mi",
"mov v16.s[0], v0.s[0]",
"msr nzcv, x20"
]
},
"vminsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0x5d 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"mov v16.16b, v17.16b",
"fcmp d17, d18",
"fcsel d0, d17, d18, mi",
"mov v16.d[0], v0.d[0]",
"msr nzcv, x20"
]
},
"vdivps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b00 0x5e 128-bit"
],
"ExpectedArm64ASM": [
"fdiv v16.4s, v17.4s, v18.4s"
]
},
"vdivps ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b00 0x5e 256-bit"
],
"ExpectedArm64ASM": [
"fdiv z16.s, p7/m, z16.s, z18.s"
]
},
"vdivps ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Aliasing source and destination",
"Map 1 0b00 0x5e 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z0, z17",
"fdiv z0.s, p7/m, z0.s, z16.s",
"mov z16.d, z0.d"
]
},
"vdivps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b00 0x5e 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"fdiv z16.s, p7/m, z16.s, z18.s"
]
},
"vdivpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x5e 128-bit"
],
"ExpectedArm64ASM": [
"fdiv v16.2d, v17.2d, v18.2d"
]
},
"vdivpd ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0x5e 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z0, z17",
"fdiv z0.d, p7/m, z0.d, z16.d",
"mov z16.d, z0.d"
]
},
"vdivpd ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0x5e 256-bit"
],
"ExpectedArm64ASM": [
"fdiv z16.d, p7/m, z16.d, z18.d"
]
},
"vdivpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x5e 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"fdiv z16.d, p7/m, z16.d, z18.d"
]
},
"vdivss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b10 0x5e 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fdiv s0, s17, s18",
"mov v16.s[0], v0.s[0]"
]
},
"vdivsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x5e 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"fdiv d0, d17, d18",
"mov v16.d[0], v0.d[0]"
]
},
"vmaxps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b00 0x5f 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v0.4s, v18.4s, v17.4s",
"mov v16.16b, v17.16b",
"bit v16.16b, v18.16b, v0.16b"
]
},
"vmaxps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b00 0x5f 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.s, p7/z, z18.s, z17.s",
"mov z0.d, z17.d",
"mov z0.s, p0/m, z18.s",
"mov z16.d, z0.d"
]
},
"vmaxpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0x5f 128-bit"
],
"ExpectedArm64ASM": [
"fcmgt v0.2d, v18.2d, v17.2d",
"mov v16.16b, v17.16b",
"bit v16.16b, v18.16b, v0.16b"
]
},
"vmaxpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x5f 256-bit"
],
"ExpectedArm64ASM": [
"fcmgt p0.d, p7/z, z18.d, z17.d",
"mov z0.d, z17.d",
"mov z0.d, p0/m, z18.d",
"mov z16.d, z0.d"
]
},
"vmaxss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b10 0x5f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"mov v16.16b, v17.16b",
"fcmp s17, s18",
"fcsel s0, s17, s18, gt",
"mov v16.s[0], v0.s[0]",
"msr nzcv, x20"
]
},
"vmaxsd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b11 0x5f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"mov v16.16b, v17.16b",
"fcmp d17, d18",
"fcsel d0, d17, d18, gt",
"mov v16.d[0], v0.d[0]",
"msr nzcv, x20"
]
},
"vpunpckhbw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x68 128-bit"
],
"ExpectedArm64ASM": [
"zip2 v16.16b, v17.16b, v18.16b"
]
},
"vpunpckhbw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x68 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.b, z17.b, z18.b",
"zip2 z3.b, z17.b, z18.b",
"mov z1.q, z2.q[1]",
"mov z16.d, z3.d",
"mov z16.b, p6/m, z1.b"
]
},
"vpunpckhwd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x69 128-bit"
],
"ExpectedArm64ASM": [
"zip2 v16.8h, v17.8h, v18.8h"
]
},
"vpunpckhwd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x69 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.h, z17.h, z18.h",
"zip2 z3.h, z17.h, z18.h",
"mov z1.q, z2.q[1]",
"mov z16.d, z3.d",
"mov z16.b, p6/m, z1.b"
]
},
"vpunpckhdq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6a 128-bit"
],
"ExpectedArm64ASM": [
"zip2 v16.4s, v17.4s, v18.4s"
]
},
"vpunpckhdq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x6a 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.s, z17.s, z18.s",
"zip2 z3.s, z17.s, z18.s",
"mov z1.q, z2.q[1]",
"mov z16.d, z3.d",
"mov z16.b, p6/m, z1.b"
]
},
"vpackssdw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0x6b 128-bit"
],
"ExpectedArm64ASM": [
"sqxtn v16.4h, v17.4s",
"sqxtn2 v16.8h, v18.4s"
]
},
"vpackssdw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 19,
"Comment": [
"Map 1 0b01 0x6b 256-bit"
],
"ExpectedArm64ASM": [
"sqxtnb z1.h, z18.s",
"uzp1 z1.h, z1.h, z1.h",
"sqxtnb z2.h, z17.s",
"uzp1 z2.h, z2.h, z2.h",
"splice z2.h, p6, z2.h, z1.h",
"mov z1.d, z2.d[1]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[2]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpunpcklqdq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6c 128-bit"
],
"ExpectedArm64ASM": [
"zip1 v16.2d, v17.2d, v18.2d"
]
},
"vpunpcklqdq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 1 0b01 0x6c 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.d, z17.d, z18.d",
"zip2 z3.d, z17.d, z18.d",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpunpckhqdq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6d 128-bit"
],
"ExpectedArm64ASM": [
"zip2 v16.2d, v17.2d, v18.2d"
]
},
"vpunpckhqdq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0x6d 256-bit"
],
"ExpectedArm64ASM": [
"zip1 z2.d, z17.d, z18.d",
"zip2 z3.d, z17.d, z18.d",
"mov z1.q, z2.q[1]",
"mov z16.d, z3.d",
"mov z16.b, p6/m, z1.b"
]
},
"vmovd xmm0, dword [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6e 128-bit"
],
"ExpectedArm64ASM": [
"ldr s16, [x4]"
]
},
"vmovq xmm0, qword [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6e 128-bit"
],
"ExpectedArm64ASM": [
"ldr d16, [x4]"
]
},
"vmovdqa xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6f 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vmovdqa [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x6f 128-bit"
],
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"vmovdqu xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x6f 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vmovdqu [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x6f 128-bit"
],
"ExpectedArm64ASM": [
"str q16, [x4]"
]
},
"vhaddpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x7c 128-bit"
],
"ExpectedArm64ASM": [
"faddp v16.2d, v17.2d, v18.2d"
]
},
"vhaddpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 19,
"Comment": [
"Map 1 0b01 0x7c 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z0, z17",
"faddp z0.d, p7/m, z0.d, z18.d",
"uzp1 z2.d, z0.d, z0.d",
"uzp2 z1.d, z0.d, z0.d",
"splice z2.d, p6, z2.d, z1.d",
"mov z1.d, z2.d[2]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[1]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vhaddps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b11 0x7c 128-bit"
],
"ExpectedArm64ASM": [
"faddp v16.4s, v17.4s, v18.4s"
]
},
"vhaddps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 19,
"Comment": [
"Map 1 0b11 0x7c 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z0, z17",
"faddp z0.s, p7/m, z0.s, z18.s",
"uzp1 z2.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z2.d, p6, z2.d, z1.d",
"mov z1.d, z2.d[2]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[1]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vhsubpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0x7d 128-bit"
],
"ExpectedArm64ASM": [
"uzp1 v2.2d, v17.2d, v18.2d",
"uzp2 v3.2d, v17.2d, v18.2d",
"fsub v16.2d, v2.2d, v3.2d"
]
},
"vhsubpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 17,
"Comment": [
"Map 1 0b01 0x7d 256-bit"
],
"ExpectedArm64ASM": [
"uzp1 z2.d, z17.d, z18.d",
"uzp2 z3.d, z17.d, z18.d",
"fsub z2.d, z2.d, z3.d",
"mov z1.d, z2.d[2]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[1]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vhsubps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0x7d 128-bit"
],
"ExpectedArm64ASM": [
"uzp1 v2.4s, v17.4s, v18.4s",
"uzp2 v3.4s, v17.4s, v18.4s",
"fsub v16.4s, v2.4s, v3.4s"
]
},
"vhsubps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 17,
"Comment": [
"Map 1 0b11 0x7d 256-bit"
],
"ExpectedArm64ASM": [
"uzp1 z2.s, z17.s, z18.s",
"uzp2 z3.s, z17.s, z18.s",
"fsub z2.s, z2.s, z3.s",
"mov z1.d, z2.d[2]",
"mov z3.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z3.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z2.d[1]",
"mov z16.d, z3.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vmovd dword [rax], xmm0": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0x7e 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"mov v0.s[0], v16.s[0]",
"mov v2.16b, v0.16b",
"str s2, [x4]"
]
},
"vmovq qword [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x7e 128-bit"
],
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"vmovdqa ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x7f 128-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vmovdqa [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0x7f 128-bit"
],
"ExpectedArm64ASM": [
"st1b {z16.b}, p7, [x4]"
]
},
"vmovdqu ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x7f 128-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vmovdqu [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b10 0x7f 128-bit"
],
"ExpectedArm64ASM": [
"st1b {z16.b}, p7, [x4]"
]
},
"vaddsubpd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2352]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.2d, v17.2d, v2.2d"
]
},
"vaddsubpd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1800]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.d, z17.d, z2.d"
]
},
"vaddsubps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b11 0xd0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2320]",
"eor v2.16b, v18.16b, v2.16b",
"fadd v16.4s, v17.4s, v2.4s"
]
},
"vaddsubps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xd0 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1784]",
"ld1b {z2.b}, p7/z, [x0]",
"eor z2.d, z18.d, z2.d",
"fadd z16.s, z17.s, z2.s"
]
},
"vpsrlw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xd1 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"lsr z2.h, p6/m, z2.h, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsrlw ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xd1 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"lsr z16.h, p7/m, z16.h, z0.d"
]
},
"vpsrld xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xd2 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"lsr z2.s, p6/m, z2.s, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsrld ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xd2 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"lsr z16.s, p7/m, z16.s, z0.d"
]
},
"vpsrlq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xd3 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"lsr z2.d, p6/m, z2.d, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsrlq ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xd3 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"lsr z16.d, p7/m, z16.d, z0.d"
]
},
"vpaddq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd4 128-bit"
],
"ExpectedArm64ASM": [
"add v16.2d, v17.2d, v18.2d"
]
},
"vpaddq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd4 256-bit"
],
"ExpectedArm64ASM": [
"add z16.d, z17.d, z18.d"
]
},
"vpmullw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd5 128-bit"
],
"ExpectedArm64ASM": [
"mul v16.8h, v17.8h, v18.8h"
]
},
"vpmullw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd4 256-bit"
],
"ExpectedArm64ASM": [
"mul z16.h, z17.h, z18.h"
]
},
"vmovq [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd6 256-bit"
],
"ExpectedArm64ASM": [
"str d16, [x4]"
]
},
"vpmovmskb rax, xmm0": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2576]",
"cmlt v3.16b, v16.16b, #0",
"and v2.16b, v3.16b, v2.16b",
"addp v2.16b, v2.16b, v2.16b",
"addp v2.8b, v2.8b, v2.8b",
"addp v2.8b, v2.8b, v2.8b",
"umov w4, v2.h[0]"
]
},
"vpmovmskb rax, ymm0": {
"ExpectedInstructionCount": 18,
"Comment": [
"Map 1 0b01 0xd7 256-bit"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1912]",
"ld1b {z2.b}, p7/z, [x0]",
"mrs x0, nzcv",
"mov z0.d, #0",
"cmplt p0.b, p7/z, z16.b, #0",
"not z0.b, p0/m, z16.b",
"orr z0.b, p0/m, z0.b, z16.b",
"mov z3.d, z0.d",
"msr nzcv, x0",
"and z2.d, z3.d, z2.d",
"movprfx z0, z2",
"addp z0.b, p7/m, z0.b, z2.b",
"uzp1 z2.b, z0.b, z0.b",
"uzp2 z1.b, z0.b, z0.b",
"splice z2.d, p6, z2.d, z1.d",
"addp v2.16b, v2.16b, v2.16b",
"addp v2.8b, v2.8b, v2.8b",
"mov w4, v2.s[0]"
]
},
"vpsubusb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd8 128-bit"
],
"ExpectedArm64ASM": [
"uqsub v16.16b, v17.16b, v18.16b"
]
},
"vpsubusb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd8 256-bit"
],
"ExpectedArm64ASM": [
"uqsub z16.b, z17.b, z18.b"
]
},
"vpsubusw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd9 128-bit"
],
"ExpectedArm64ASM": [
"uqsub v16.8h, v17.8h, v18.8h"
]
},
"vpsubusw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xd9 256-bit"
],
"ExpectedArm64ASM": [
"uqsub z16.h, z17.h, z18.h"
]
},
"vpminub xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xda 128-bit"
],
"ExpectedArm64ASM": [
"umin v16.16b, v17.16b, v18.16b"
]
},
"vpminub ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xda 256-bit"
],
"ExpectedArm64ASM": [
"umin z16.b, p7/m, z16.b, z17.b"
]
},
"vpminub ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xda 256-bit"
],
"ExpectedArm64ASM": [
"umin z16.b, p7/m, z16.b, z18.b"
]
},
"vpminub ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xda 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"umin z16.b, p7/m, z16.b, z18.b"
]
},
"vpand xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdb 128-bit"
],
"ExpectedArm64ASM": [
"and v16.16b, v17.16b, v18.16b"
]
},
"vpand ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdb 256-bit"
],
"ExpectedArm64ASM": [
"and z16.d, z17.d, z18.d"
]
},
"vpaddusb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdc 128-bit"
],
"ExpectedArm64ASM": [
"uqadd v16.16b, v17.16b, v18.16b"
]
},
"vpaddusb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdc 256-bit"
],
"ExpectedArm64ASM": [
"uqadd z16.b, z17.b, z18.b"
]
},
"vpaddusw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdd 128-bit"
],
"ExpectedArm64ASM": [
"uqadd v16.8h, v17.8h, v18.8h"
]
},
"vpaddusw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdd 256-bit"
],
"ExpectedArm64ASM": [
"uqadd z16.h, z17.h, z18.h"
]
},
"vpmaxub xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xdd 128-bit"
],
"ExpectedArm64ASM": [
"umax v16.16b, v17.16b, v18.16b"
]
},
"vpmaxub ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xde 256-bit"
],
"ExpectedArm64ASM": [
"umax z16.b, p7/m, z16.b, z18.b"
]
},
"vpmaxub ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xde 256-bit"
],
"ExpectedArm64ASM": [
"umax z16.b, p7/m, z16.b, z17.b"
]
},
"vpmaxub ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xde 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"umax z16.b, p7/m, z16.b, z18.b"
]
},
"vpandn xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"bic v16.16b, v18.16b, v17.16b"
]
},
"vpandn ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xdf 256-bit"
],
"ExpectedArm64ASM": [
"bic z16.d, z18.d, z17.d"
]
},
"vpavgb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe0 128-bit"
],
"ExpectedArm64ASM": [
"urhadd v16.16b, v17.16b, v18.16b"
]
},
"vpavgb ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xe0 256-bit"
],
"ExpectedArm64ASM": [
"urhadd z16.b, p7/m, z16.b, z17.b"
]
},
"vpavgb ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xe0 256-bit"
],
"ExpectedArm64ASM": [
"urhadd z16.b, p7/m, z16.b, z18.b"
]
},
"vpavgb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xe0 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"urhadd z16.b, p7/m, z16.b, z18.b"
]
},
"vpsraw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xe1 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"asr z2.h, p6/m, z2.h, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsraw ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe1 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"asr z16.h, p7/m, z16.h, z0.d"
]
},
"vpsrad xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xe2 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"asr z2.s, p6/m, z2.s, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsrad ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe2 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"asr z16.s, p7/m, z16.s, z0.d"
]
},
"vpavgw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe3 128-bit"
],
"ExpectedArm64ASM": [
"urhadd v16.8h, v17.8h, v18.8h"
]
},
"vpavgw ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xe3 256-bit"
],
"ExpectedArm64ASM": [
"urhadd z16.h, p7/m, z16.h, z17.h"
]
},
"vpavgw ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xe3 256-bit"
],
"ExpectedArm64ASM": [
"urhadd z16.h, p7/m, z16.h, z18.h"
]
},
"vpavgw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xe3 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"urhadd z16.h, p7/m, z16.h, z18.h"
]
},
"vpmulhuw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe4 128-bit"
],
"ExpectedArm64ASM": [
"movprfx z2, z17",
"umulh z2.h, p6/m, z2.h, z18.h",
"mov v16.16b, v2.16b"
]
},
"vpmulhuw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe4 256-bit"
],
"ExpectedArm64ASM": [
"umulh z16.h, z17.h, z18.h"
]
},
"vpmulhw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe5 128-bit"
],
"ExpectedArm64ASM": [
"movprfx z2, z17",
"smulh z2.h, p6/m, z2.h, z18.h",
"mov v16.16b, v2.16b"
]
},
"vpmulhw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe5 256-bit"
],
"ExpectedArm64ASM": [
"smulh z16.h, z17.h, z18.h"
]
},
"vcvttpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"fcvtzs z16.s, p6/m, z17.d",
"uzp1 z16.s, z16.s, z16.s",
"mov v16.8b, v16.8b"
]
},
"vcvttpd2dq xmm0, ymm1": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"fcvtzs z16.s, p7/m, z17.d",
"uzp1 z16.s, z16.s, z16.s",
"mov v16.16b, v16.16b"
]
},
"vcvtdq2pd xmm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"sxtl v2.2d, v17.2s",
"scvtf v16.2d, v2.2d"
]
},
"vcvtdq2pd ymm0, xmm1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b10 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"sunpklo z2.d, z17.s",
"scvtf z16.d, p7/m, z2.d"
]
},
"vcvtpd2dq xmm0, xmm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xe6 128-bit"
],
"ExpectedArm64ASM": [
"frinti z16.d, p6/m, z17.d",
"fcvtzs z16.s, p6/m, z16.d",
"uzp1 z16.s, z16.s, z16.s",
"mov v16.8b, v16.8b"
]
},
"vcvtpd2dq xmm0, ymm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b11 0xe6 256-bit"
],
"ExpectedArm64ASM": [
"frinti z16.d, p7/m, z17.d",
"fcvtzs z16.s, p7/m, z16.d",
"uzp1 z16.s, z16.s, z16.s",
"mov v16.16b, v16.16b"
]
},
"vmovntdq [rax], xmm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe7 128-bit"
],
"ExpectedArm64ASM": [
"stnt1b {z16.b}, p6, [x4]"
]
},
"vmovntdq [rax], ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe7 256-bit"
],
"ExpectedArm64ASM": [
"stnt1b {z16.b}, p7, [x4]"
]
},
"vpsubsb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe8 128-bit"
],
"ExpectedArm64ASM": [
"sqsub v16.16b, v17.16b, v18.16b"
]
},
"vpsubsb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe8 256-bit"
],
"ExpectedArm64ASM": [
"sqsub z16.b, z17.b, z18.b"
]
},
"vpsubsw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe9 128-bit"
],
"ExpectedArm64ASM": [
"sqsub v16.8h, v17.8h, v18.8h"
]
},
"vpsubsw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xe9 256-bit"
],
"ExpectedArm64ASM": [
"sqsub z16.h, z17.h, z18.h"
]
},
"vpminsw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xea 128-bit"
],
"ExpectedArm64ASM": [
"smin v16.8h, v17.8h, v18.8h"
]
},
"vpminsw ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xea 256-bit"
],
"ExpectedArm64ASM": [
"smin z16.h, p7/m, z16.h, z17.h"
]
},
"vpminsw ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xea 256-bit"
],
"ExpectedArm64ASM": [
"smin z16.h, p7/m, z16.h, z18.h"
]
},
"vpminsw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xea 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"smin z16.h, p7/m, z16.h, z18.h"
]
},
"vpor xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xeb 128-bit"
],
"ExpectedArm64ASM": [
"orr v16.16b, v17.16b, v18.16b"
]
},
"vpor ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xeb 256-bit"
],
"ExpectedArm64ASM": [
"orr z16.d, z17.d, z18.d"
]
},
"vpaddsb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xec 128-bit"
],
"ExpectedArm64ASM": [
"sqadd v16.16b, v17.16b, v18.16b"
]
},
"vpaddsb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xec 256-bit"
],
"ExpectedArm64ASM": [
"sqadd z16.b, z17.b, z18.b"
]
},
"vpaddsw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xed 128-bit"
],
"ExpectedArm64ASM": [
"sqadd v16.8h, v17.8h, v18.8h"
]
},
"vpaddsw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xed 256-bit"
],
"ExpectedArm64ASM": [
"sqadd z16.h, z17.h, z18.h"
]
},
"vpmaxsw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xee 128-bit"
],
"ExpectedArm64ASM": [
"smax v16.8h, v17.8h, v18.8h"
]
},
"vpmaxsw ymm0, ymm1, ymm0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xee 256-bit"
],
"ExpectedArm64ASM": [
"smax z16.h, p7/m, z16.h, z17.h"
]
},
"vpmaxsw ymm0, ymm0, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Aliasing source and destination",
"Map 1 0b01 0xee 256-bit"
],
"ExpectedArm64ASM": [
"smax z16.h, p7/m, z16.h, z18.h"
]
},
"vpmaxsw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 1 0b01 0xee 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z16, z17",
"smax z16.h, p7/m, z16.h, z18.h"
]
},
"vpxor xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xef 128-bit"
],
"ExpectedArm64ASM": [
"eor v16.16b, v17.16b, v18.16b"
]
},
"vpxor ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xef 256-bit"
],
"ExpectedArm64ASM": [
"eor z16.d, z17.d, z18.d"
]
},
"vpxor xmm0, xmm1, xmm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"xor with itself to get zero register",
"Map 1 0b01 0xef 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vpxor ymm0, ymm1, ymm1": {
"ExpectedInstructionCount": 1,
"Comment": [
"xor with itself to get zero register",
"Map 1 0b01 0xef 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vlddqu xmm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b11 0xf0 128-bit"
],
"ExpectedArm64ASM": [
"ldr q16, [x4]"
]
},
"vlddqu ymm0, [rax]": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b11 0xf0 256-bit"
],
"ExpectedArm64ASM": [
"ld1b {z16.b}, p7/z, [x4]"
]
},
"vpsllw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xf1 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"lsl z2.h, p6/m, z2.h, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsllw ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xf1 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"lsl z16.h, p7/m, z16.h, z0.d"
]
},
"vpslld xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xf2 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"lsl z2.s, p6/m, z2.s, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpslld ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xf2 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"lsl z16.s, p7/m, z16.s, z0.d"
]
},
"vpsllq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xf3 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z2, z17",
"lsl z2.d, p6/m, z2.d, z0.d",
"mov v16.16b, v2.16b"
]
},
"vpsllq ymm0, ymm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xf3 256-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, d18",
"movprfx z16, z17",
"lsl z16.d, p7/m, z16.d, z0.d"
]
},
"vpmuludq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xf4 128-bit"
],
"ExpectedArm64ASM": [
"uzp1 v2.4s, v17.4s, v17.4s",
"uzp1 v3.4s, v18.4s, v18.4s",
"umull v16.2d, v2.2s, v3.2s"
]
},
"vpmuludq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0xf4 256-bit"
],
"ExpectedArm64ASM": [
"uzp1 z2.s, z17.s, z17.s",
"uzp1 z3.s, z18.s, z18.s",
"umullb z0.d, z2.s, z3.s",
"umullt z1.d, z2.s, z3.s",
"zip1 z16.d, z0.d, z1.d"
]
},
"vpmaddwd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 1 0b01 0xf5 128-bit"
],
"ExpectedArm64ASM": [
"smull v2.4s, v17.4h, v18.4h",
"smull2 v3.4s, v17.8h, v18.8h",
"addp v16.4s, v2.4s, v3.4s"
]
},
"vpmaddwd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 1 0b01 0xf5 256-bit"
],
"ExpectedArm64ASM": [
"smullb z0.s, z17.h, z18.h",
"smullt z1.s, z17.h, z18.h",
"zip1 z2.s, z0.s, z1.s",
"smullb z0.s, z17.h, z18.h",
"smullt z1.s, z17.h, z18.h",
"zip2 z3.s, z0.s, z1.s",
"movprfx z0, z2",
"addp z0.s, p7/m, z0.s, z3.s",
"uzp1 z16.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z16.d, p6, z16.d, z1.d"
]
},
"vpsadbw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 1 0b01 0xf6 128-bit"
],
"ExpectedArm64ASM": [
"uabdl v2.8h, v17.8b, v18.8b",
"uabdl2 v3.8h, v17.16b, v18.16b",
"addv h2, v2.8h",
"addv h3, v3.8h",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"vpsadbw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 36,
"Comment": [
"Map 1 0b01 0xf6 256-bit"
],
"ExpectedArm64ASM": [
"uabdlb z0.h, z17.b, z18.b",
"uabdlt z1.h, z17.b, z18.b",
"zip1 z2.h, z0.h, z1.h",
"uabdlb z0.h, z17.b, z18.b",
"uabdlt z1.h, z17.b, z18.b",
"zip2 z3.h, z0.h, z1.h",
"addv h4, v2.8h",
"addv h5, v3.8h",
"zip1 z4.d, z4.d, z5.d",
"mov z2.q, z2.q[1]",
"mov z3.q, z3.q[1]",
"addv h2, v2.8h",
"addv h3, v3.8h",
"mov z1.d, d3",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.q, q2",
"not p0.b, p7/z, p6.b",
"mov z4.b, p0/m, z1.b",
"mov z1.d, z4.d[1]",
"mov z2.d, z4.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z4.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vmaskmovdqu xmm0, xmm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 1 0b01 0xf7 128-bit"
],
"ExpectedArm64ASM": [
"cmlt v2.16b, v17.16b, #0",
"ldr q3, [x11]",
"bsl v2.16b, v16.16b, v3.16b",
"str q2, [x11]"
]
},
"vpsubb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xf8 128-bit"
],
"ExpectedArm64ASM": [
"sub v16.16b, v17.16b, v18.16b"
]
},
"vpsubb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xf8 256-bit"
],
"ExpectedArm64ASM": [
"sub z16.b, z17.b, z18.b"
]
},
"vpsubw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xf9 128-bit"
],
"ExpectedArm64ASM": [
"sub v16.8h, v17.8h, v18.8h"
]
},
"vpsubw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xf9 256-bit"
],
"ExpectedArm64ASM": [
"sub z16.h, z17.h, z18.h"
]
},
"vpsubd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfa 128-bit"
],
"ExpectedArm64ASM": [
"sub v16.4s, v17.4s, v18.4s"
]
},
"vpsubd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfa 256-bit"
],
"ExpectedArm64ASM": [
"sub z16.s, z17.s, z18.s"
]
},
"vpsubq xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfb 128-bit"
],
"ExpectedArm64ASM": [
"sub v16.2d, v17.2d, v18.2d"
]
},
"vpsubq ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfb 256-bit"
],
"ExpectedArm64ASM": [
"sub z16.d, z17.d, z18.d"
]
},
"vpaddb xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfc 128-bit"
],
"ExpectedArm64ASM": [
"add v16.16b, v17.16b, v18.16b"
]
},
"vpaddb ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfc 256-bit"
],
"ExpectedArm64ASM": [
"add z16.b, z17.b, z18.b"
]
},
"vpaddw xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfd 128-bit"
],
"ExpectedArm64ASM": [
"add v16.8h, v17.8h, v18.8h"
]
},
"vpaddw ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfd 256-bit"
],
"ExpectedArm64ASM": [
"add z16.h, z17.h, z18.h"
]
},
"vpaddd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfe 128-bit"
],
"ExpectedArm64ASM": [
"add v16.4s, v17.4s, v18.4s"
]
},
"vpaddd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 1 0b01 0xfe 256-bit"
],
"ExpectedArm64ASM": [
"add z16.s, z17.s, z18.s"
]
}
}
}
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