Alyssa Rosenzweig 82ba16c6ed OpcodeDispatcher: optimize LOOP/N/E ...

Don't clobber NZCV.

Before/after assembly from the Primary_E1 unit test:

< 4340: [INFO] cset w20, ne
< 4340: [INFO] mrs x21, nzcv
< 4340: [INFO] cmp x5, #0x0 (0)
< 4340: [INFO] cset x22, ne
< 4340: [INFO] and x20, x22, x20
< 4340: [INFO] msr nzcv, x21
< 4340: [INFO] cbnz x20, #+0x8 (addr 0xffff896f8084)
< 4340: [INFO] b #+0x1c (addr 0xffff896f809c)
< 4340: [INFO] ldr x0, pc+8 (addr 0xffff896f808c)
---
> 4340: [INFO] csel x20, x5, xzr, ne
> 4340: [INFO] cbnz x20, #+0x8 (addr 0xfffed7308070)
> 4340: [INFO] b #+0x1c (addr 0xfffed7308088)
> 4340: [INFO] ldr x0, pc+8 (addr 0xfffed7308078)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-03-21 12:08:40 -04:00

..

Config

Implement small TSC scaling

2024-02-20 12:05:44 -08:00

Context

Disable assert in release

2024-03-10 22:01:50 -07:00

Core

OpcodeDispatcher: optimize LOOP/N/E

2024-03-21 12:08:40 -04:00

GDBJIT

FEXCore/Interface/GDBJIT: Adds SPDX identifier

2023-09-19 17:33:15 -07:00

HLE/Thunks

Library Forwarding: Allocate packed arguments on the guest stack if needed

2024-02-05 18:10:34 +01:00

IR

Merge pull request #3492 from Sonicadvance1/implement_prefetch

2024-03-18 07:49:47 -04:00