mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-01-27 01:04:55 +00:00
617977357a
This needs to default to 64-bit addresses, this was previously defaulting to 32-bit which was meaning the destination address was getting truncated. In a 32-bit process the address is still 32-bit. I'm actually surprised this hasn't caused spurious SIGSEGV before this point. Adds a 32-bit test to ensure that side is tested as well.
94 lines
1.8 KiB
NASM
94 lines
1.8 KiB
NASM
%ifdef CONFIG
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{
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"RegData": {
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"RBX": "0x0",
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"RCX": "0x000000000a121a20",
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"RDX": "0x000000000b131b20"
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},
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"Mode": "32BIT",
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"HostFeatures": ["CLZERO"]
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}
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%endif
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; Starting address to store to
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mov eax, 0xe8000000
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; Set up the cachelines with garbage
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; Cacheline 0
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mov ebx, 0x41424344
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mov [eax + 8 * 0], ebx
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mov [eax + 8 * 1], ebx
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mov [eax + 8 * 2], ebx
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mov [eax + 8 * 3], ebx
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mov [eax + 8 * 4], ebx
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mov [eax + 8 * 5], ebx
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mov [eax + 8 * 6], ebx
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mov [eax + 8 * 7], ebx
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; Cacheline 1
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mov ebx, 0x55565758
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mov [eax + 8 * 8], ebx
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mov [eax + 8 * 9], ebx
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mov [eax + 8 * 10], ebx
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mov [eax + 8 * 11], ebx ; clzero here
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mov [eax + 8 * 12], ebx
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mov [eax + 8 * 13], ebx
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mov [eax + 8 * 14], ebx
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mov [eax + 8 * 15], ebx
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; Cacheline 2
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mov ebx, 0x61626364
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mov [eax + 8 * 16], ebx
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mov [eax + 8 * 17], ebx
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mov [eax + 8 * 18], ebx
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mov [eax + 8 * 19], ebx
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mov [eax + 8 * 20], ebx
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mov [eax + 8 * 21], ebx
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mov [eax + 8 * 22], ebx
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mov [eax + 8 * 23], ebx
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; Set RAX to the middle of cacheline 1 to ensure alignment
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lea eax, [eax + 8 * 11]
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clzero
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; Set eax back to the start
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mov eax, 0xe8000000
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mov ebx, 0
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mov ecx, 0
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mov edx, 0
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; Cacheline 0 should be unmodified
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add ecx, [eax + 8 * 0]
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add ecx, [eax + 8 * 1]
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add ecx, [eax + 8 * 2]
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add ecx, [eax + 8 * 3]
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add ecx, [eax + 8 * 4]
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add ecx, [eax + 8 * 5]
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add ecx, [eax + 8 * 6]
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add ecx, [eax + 8 * 7]
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; Cacheline 1 Should be zero
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add ebx, [eax + 8 * 8]
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add ebx, [eax + 8 * 9]
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add ebx, [eax + 8 * 10]
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add ebx, [eax + 8 * 11]
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add ebx, [eax + 8 * 12]
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add ebx, [eax + 8 * 13]
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add ebx, [eax + 8 * 14]
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add ebx, [eax + 8 * 15]
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; Cacheline 2 should be unmodified
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add edx, [eax + 8 * 16]
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add edx, [eax + 8 * 17]
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add edx, [eax + 8 * 18]
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add edx, [eax + 8 * 19]
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add edx, [eax + 8 * 20]
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add edx, [eax + 8 * 21]
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add edx, [eax + 8 * 22]
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add edx, [eax + 8 * 23]
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hlt
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