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3d23cd5765
In the event no source vectors alias the destination, we can just move the first source vector into it and then perform the divide without needing to move afterword.
53 lines
1.5 KiB
NASM
53 lines
1.5 KiB
NASM
%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM0": ["0x3FF0000000000000", "0x3FF0000000000000", "0x3FF0000000000000", "0x3FF0000000000000"],
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"XMM1": ["0x4000000000000000", "0x4000000000000000", "0x4000000000000000", "0x4000000000000000"],
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"XMM2": ["0x3FE0000000000000", "0x3FE0000000000000", "0x0000000000000000", "0x0000000000000000"],
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"XMM3": ["0x3FE0000000000000", "0x3FE0000000000000", "0x0000000000000000", "0x0000000000000000"],
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"XMM4": ["0x3FE0000000000000", "0x3FE0000000000000", "0x3FE0000000000000", "0x3FE0000000000000"],
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"XMM5": ["0x4000000000000000", "0x4000000000000000", "0x4000000000000000", "0x4000000000000000"],
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"XMM6": ["0x3FE0000000000000", "0x3FE0000000000000", "0x3FE0000000000000", "0x3FE0000000000000"],
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"XMM7": ["0x4000000000000000", "0x4000000000000000", "0x4000000000000000", "0x4000000000000000"]
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},
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"MemoryRegions": {
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"0x100000000": "4096"
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}
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}
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%endif
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lea rdx, [rel .data]
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vmovapd ymm0, [rdx]
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vmovapd ymm1, [rdx + 32]
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; Memory operand
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vdivpd xmm2, xmm0, [rdx + 32]
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vdivpd ymm4, ymm0, [rdx + 32]
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; Register only
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vdivpd xmm3, xmm0, xmm1
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vdivpd ymm5, ymm1, ymm0
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; Some tests for aliasing destination and source vectors
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vmovapd ymm6, ymm0
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vdivpd ymm6, ymm6, ymm1
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vmovapd ymm7, ymm0
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vdivpd ymm7, ymm1, ymm7
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hlt
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align 32
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.data:
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dq 0x3FF0000000000000
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dq 0x3FF0000000000000
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dq 0x3FF0000000000000
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dq 0x3FF0000000000000
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dq 0x4000000000000000
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dq 0x4000000000000000
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dq 0x4000000000000000
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dq 0x4000000000000000
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