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bf1e619ead
Now that we have some AVX instructions in place, we can make the test use them and also enforce correctness behavior in the upper lane.
51 lines
1.4 KiB
NASM
51 lines
1.4 KiB
NASM
%ifdef CONFIG
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{
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"HostFeatures": ["AVX"],
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"RegData": {
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"XMM1": ["0xA76C4F06A12BFCE0", "0x9B80767F1E6A060F", "0xFFFFFFFFFFFFFFFF", "0xEEEEEEEEEEEEEEEE"],
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"XMM2": ["0x6868C3F3AAED56E0", "0xF0FCE9E294E6E6DE", "0xDDDDDDDDDDDDDDDD", "0xCCCCCCCCCCCCCCCC"],
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"XMM3": ["0x1E2017C5BEE29400", "0x38358E40CC367C7A", "0x0000000000000000", "0x0000000000000000"],
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"XMM4": ["0xE208147952DE57A0", "0x317D360F86C80DC9", "0x0000000000000000", "0x0000000000000000"],
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"XMM5": ["0xBBA54C87DA872B40", "0x6495428B7641EBE6", "0x0000000000000000", "0x0000000000000000"],
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"XMM6": ["0x170B5A1B5CDD42EA", "0x719F094BB2358CA1", "0x0000000000000000", "0x0000000000000000"]
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}
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}
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%endif
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lea rdx, [rel .data]
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; Load inputs
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vmovaps ymm1, [rdx + 32 * 0]
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vmovaps ymm2, [rdx + 32 * 1]
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; Fill result vectors with junk (ensure proper lane clearing is performed)
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vmovaps ymm3, [rdx + 32 * 0]
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vmovaps ymm4, [rdx + 32 * 0]
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vmovaps ymm5, [rdx + 32 * 0]
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vmovaps ymm6, [rdx + 32 * 0]
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; With imm = 0b00000000
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vpclmulqdq xmm3, xmm1, xmm2, 0
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; With imm = 0b00000001
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vpclmulqdq xmm4, xmm1, xmm2, 1
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; With imm = 0b00010000
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vpclmulqdq xmm5, xmm1, xmm2, 16
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; With imm = 0b00010001
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vpclmulqdq xmm6, xmm1, xmm2, 17
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hlt
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align 32
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.data:
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dq 0xA76C4F06A12BFCE0
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dq 0x9B80767F1E6A060F
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dq 0xFFFFFFFFFFFFFFFF
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dq 0xEEEEEEEEEEEEEEEE
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dq 0x6868C3F3AAED56E0
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dq 0xF0FCE9E294E6E6DE
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dq 0xDDDDDDDDDDDDDDDD
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dq 0xCCCCCCCCCCCCCCCC
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