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FEX/unittests/InstructionCountCI/VEX_map3.json
Alyssa Rosenzweig cf834aa6da InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-06-26 16:46:21 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"SVE256",
"SVE128"
],
"DisabledHostFeatures": [
"AFP"
]
},
"Instructions": {
"vpermq ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, d17"
]
},
"vpermq ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, z17.d[1]"
]
},
"vpermq ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, z17.d[2]"
]
},
"vpermq ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x00 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, z17.d[3]"
]
},
"vpermpd ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, d17"
]
},
"vpermpd ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, z17.d[1]"
]
},
"vpermpd ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, z17.d[2]"
]
},
"vpermpd ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x01 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, z17.d[3]"
]
},
"vpblendd xmm0, xmm1, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b"
]
},
"vpblendd xmm0, xmm1, 0001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 0010b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 0011b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 0100b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 0101b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 0110b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 0111b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v16.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1000b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1010b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1011b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v16.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1100b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1101b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v16.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1110b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v16.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vpblendd xmm0, xmm1, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x02 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vpblendd ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 0,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": []
},
"vpblendd ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[7]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpblendd ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, s16",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z16.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpblendd ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x02 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z17.d"
]
},
"vpermilps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[0]",
"mov v2.s[1], v17.s[0]",
"mov v2.s[2], v17.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[0]"
]
},
"vpermilps xmm0, xmm1, 01010101b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[1]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v17.s[1]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[1]"
]
},
"vpermilps xmm0, xmm1, 10101010b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[2]",
"mov v2.s[1], v17.s[2]",
"mov v2.s[2], v17.s[2]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[2]"
]
},
"vpermilps xmm0, xmm1, 11111111b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x03 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v17.s[3]",
"mov v2.s[1], v17.s[3]",
"mov v2.s[2], v17.s[3]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v17.s[3]"
]
},
"vpermilps ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s17",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpermilps ymm0, ymm1, 01010101b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, z17.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpermilps ymm0, ymm1, 10101010b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, z17.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpermilps ymm0, ymm1, 11111111b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x03 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, z17.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[7]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vpermilpd xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.d[0], v17.d[0]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[0]"
]
},
"vpermilpd xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.d[0], v17.d[1]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[0]"
]
},
"vpermilpd xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.d[0], v17.d[0]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"vpermilpd xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x05 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.d[0], v17.d[1]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"vpermilpd ymm0, ymm1, 0000b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0001b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0010b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0011b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0100b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0101b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0110b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 0111b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1000b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1001b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1010b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1011b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1100b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1101b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1110b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vpermilpd ymm0, ymm1, 1111b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x05 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00000011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00010011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00100011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00110011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00001000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00011000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00101000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 00111000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10001000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000000b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000001b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vperm2f128 ymm0, ymm1, ymm2, 10000011b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x06 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vroundps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintn v16.4s, v17.4s"
]
},
"vroundps xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintm v16.4s, v17.4s"
]
},
"vroundps xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintp v16.4s, v17.4s"
]
},
"vroundps xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frintz v16.4s, v17.4s"
]
},
"vroundps xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x08 128-bit"
],
"ExpectedArm64ASM": [
"frinti v16.4s, v17.4s"
]
},
"vroundps ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"frintn z16.s, p7/m, z17.s"
]
},
"vroundps ymm0, ymm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"frintm z16.s, p7/m, z17.s"
]
},
"vroundps ymm0, ymm1, 00000010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"frintp z16.s, p7/m, z17.s"
]
},
"vroundps ymm0, ymm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"frintz z16.s, p7/m, z17.s"
]
},
"vroundps ymm0, ymm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x08 256-bit"
],
"ExpectedArm64ASM": [
"frinti z16.s, p7/m, z17.s"
]
},
"vroundpd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintn v16.2d, v17.2d"
]
},
"vroundpd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintm v16.2d, v17.2d"
]
},
"vroundpd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintp v16.2d, v17.2d"
]
},
"vroundpd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frintz v16.2d, v17.2d"
]
},
"vroundpd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x09 128-bit"
],
"ExpectedArm64ASM": [
"frinti v16.2d, v17.2d"
]
},
"vroundpd ymm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"frintn z16.d, p7/m, z17.d"
]
},
"vroundpd ymm0, ymm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"frintm z16.d, p7/m, z17.d"
]
},
"vroundpd ymm0, ymm1, 00000010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"frintp z16.d, p7/m, z17.d"
]
},
"vroundpd ymm0, ymm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"frintz z16.d, p7/m, z17.d"
]
},
"vroundpd ymm0, ymm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x09 256-bit"
],
"ExpectedArm64ASM": [
"frinti z16.d, p7/m, z17.d"
]
},
"vroundss xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintn s0, s16",
"mov v16.s[0], v0.s[0]"
]
},
"vroundss xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintm s0, s16",
"mov v16.s[0], v0.s[0]"
]
},
"vroundss xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintp s0, s16",
"mov v16.s[0], v0.s[0]"
]
},
"vroundss xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintz s0, s16",
"mov v16.s[0], v0.s[0]"
]
},
"vroundss xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 3,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x0a 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frinti s0, s16",
"mov v16.s[0], v0.s[0]"
]
},
"vroundsd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 3,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintn d0, d16",
"mov v16.d[0], v0.d[0]"
]
},
"vroundsd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 3,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintm d0, d16",
"mov v16.d[0], v0.d[0]"
]
},
"vroundsd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 3,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintp d0, d16",
"mov v16.d[0], v0.d[0]"
]
},
"vroundsd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 3,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frintz d0, d16",
"mov v16.d[0], v0.d[0]"
]
},
"vroundsd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 3,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x0b 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v16.16b",
"frinti d0, d16",
"mov v16.d[0], v0.d[0]"
]
},
"vblendps xmm0, xmm1, xmm2, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vblendps xmm0, xmm1, xmm2, 0001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 3 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.s[0], v18.s[0]",
"mov v2.s[1], v17.s[1]",
"mov v2.s[2], v17.s[2]",
"mov v2.s[3], v17.s[3]",
"mov v16.16b, v2.16b"
]
},
"vblendps xmm0, xmm1, xmm2, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0c 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v18.16b"
]
},
"vblendps ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0c 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z17.d"
]
},
"vblendps ymm0, ymm1, ymm2, 10000001b": {
"ExpectedInstructionCount": 50,
"Comment": [
"Map 3 0b01 0x0c 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.s, s18",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[1]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[2]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[3]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[4]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[5]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z17.s[6]",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, z18.s[7]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vblendps ymm0, ymm1, ymm2, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0c 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z18.d"
]
},
"vblendpd xmm0, xmm1, xmm2, 00b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vblendpd xmm0, xmm1, xmm2, 01b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.d[0], v18.d[0]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v17.d[1]"
]
},
"vblendpd xmm0, xmm1, xmm2, 10b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.d[0], v17.d[0]",
"mov v16.16b, v2.16b",
"mov v16.d[1], v18.d[1]"
]
},
"vblendpd xmm0, xmm1, xmm2, 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0d 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v18.16b"
]
},
"vblendpd ymm0, ymm1, ymm2, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z17.d"
]
},
"vblendpd ymm0, ymm1, ymm2, 0001b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 0010b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 0011b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 0100b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 0101b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 0110b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 0111b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1000b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1001b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1010b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1011b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1100b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1101b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d18",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z17.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1110b": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.d, d17",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-2",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[1]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #-1",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[2]",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #0",
"mov z2.d, p0/m, z1.d",
"msr nzcv, x0",
"mov z1.d, z18.d[3]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.d, #-2, #1",
"cmpeq p0.d, p7/z, z0.d, #1",
"mov z16.d, p0/m, z1.d",
"msr nzcv, x0"
]
},
"vblendpd ymm0, ymm1, ymm2, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0d 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z18.d"
]
},
"vpblendw xmm0, xmm1, xmm2, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vpblendw xmm0, xmm1, xmm2, 00000001b": {
"ExpectedInstructionCount": 10,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov v2.h[0], v18.h[0]",
"mov v2.h[1], v17.h[1]",
"mov v2.h[2], v17.h[2]",
"mov v2.h[3], v17.h[3]",
"mov v2.h[4], v17.h[4]",
"mov v2.h[5], v17.h[5]",
"mov v2.h[6], v17.h[6]",
"mov v2.h[7], v17.h[7]",
"mov v16.16b, v2.16b"
]
},
"vpblendw xmm0, xmm1, xmm2, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v18.16b"
]
},
"vpblendw ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z17.d"
]
},
"vpblendw ymm0, ymm1, ymm2, 00000001b": {
"ExpectedInstructionCount": 98,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.h, h18",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-8",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[1]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-7",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[2]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[3]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[4]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[5]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-3",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[6]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[7]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #-1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z18.h[8]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #0",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[9]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #1",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[10]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #2",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[11]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #3",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[12]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #4",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[13]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #5",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[14]",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #6",
"mov z2.h, p0/m, z1.h",
"msr nzcv, x0",
"mov z1.h, z17.h[15]",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.h, #-8, #1",
"cmpeq p0.h, p7/z, z0.h, #7",
"mov z16.h, p0/m, z1.h",
"msr nzcv, x0"
]
},
"vpblendw ymm0, ymm1, ymm2, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0e 128-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z18.d"
]
},
"vpalignr xmm0, xmm1, xmm2, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v18.16b"
]
},
"vpalignr xmm0, xmm1, xmm2, 1": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v18.16b, v17.16b, #1"
]
},
"vpalignr xmm0, xmm1, xmm2, 15": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"ext v16.16b, v18.16b, v17.16b, #15"
]
},
"vpalignr xmm0, xmm1, xmm2, 16": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x0f 128-bit"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"ext v16.16b, v17.16b, v0.16b, #0"
]
},
"vpalignr ymm0, ymm1, ymm2, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"mov z16.d, p7/m, z18.d"
]
},
"vpalignr ymm0, ymm1, ymm2, 1": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ext v2.16b, v18.16b, v17.16b, #1",
"mov z1.q, z17.q[1]",
"mov z3.d, z17.d",
"mov z3.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z4.d, z18.d",
"mov z4.b, p6/m, z1.b",
"ext v3.16b, v4.16b, v3.16b, #1",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpalignr ymm0, ymm1, ymm2, 15": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"ext v2.16b, v18.16b, v17.16b, #15",
"mov z1.q, z17.q[1]",
"mov z3.d, z17.d",
"mov z3.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z4.d, z18.d",
"mov z4.b, p6/m, z1.b",
"ext v3.16b, v4.16b, v3.16b, #15",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpalignr ymm0, ymm1, ymm2, 16": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x0f 256-bit"
],
"ExpectedArm64ASM": [
"movi v0.2d, #0x0",
"ext v2.16b, v17.16b, v0.16b, #0",
"mov z1.q, z17.q[1]",
"mov z3.d, z17.d",
"mov z3.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z4.d, z18.d",
"mov z4.b, p6/m, z1.b",
"movi v0.2d, #0x0",
"ext v3.16b, v3.16b, v0.16b, #0",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpextrb rax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.b[0]"
]
},
"vpextrb rax, xmm0, 15": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.b[15]"
]
},
"vpextrw rax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[0]"
]
},
"vpextrw rax, xmm0, 7": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[7]"
]
},
"vpextrd rax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[0]"
]
},
"vpextrd rax, xmm0, 3": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[3]"
]
},
"vpextrb [rax], xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.b}[0], [x4]"
]
},
"vpextrb [rax], xmm0, 15": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x14 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.b}[15], [x4]"
]
},
"vpextrw [rax], xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[0], [x4]"
]
},
"vpextrw [rax], xmm0, 7": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x15 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[7], [x4]"
]
},
"vpextrd [rax], xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.s}[0], [x4]"
]
},
"vpextrd [rax], xmm0, 3": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x16 128-bit"
],
"ExpectedArm64ASM": [
"st1 {v16.s}[3], [x4]"
]
},
"vextractps eax, xmm0, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x17 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[0]"
]
},
"vextractps eax, xmm0, 3": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x17 128-bit"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[3]"
]
},
"vinsertf128 ymm0, ymm1, xmm2, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x18 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.q, q18",
"mov z16.d, z17.d",
"mov z16.b, p6/m, z1.b"
]
},
"vinsertf128 ymm0, ymm1, xmm2, 1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x18 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.q, q18",
"mov z16.d, z17.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vextractf128 xmm0, ymm1, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x19 256-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vextractf128 xmm0, ymm1, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x19 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"mov v16.16b, v2.16b"
]
},
"vcvtps2ph xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20"
]
},
"vcvtps2ph xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 6,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffffbfffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20"
]
},
"vcvtps2ph xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 6,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff7fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20"
]
},
"vcvtps2ph xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 5,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"orr x0, x20, #0xc00000",
"msr fpcr, x0",
"fcvtn v16.4h, v17.4s",
"msr fpcr, x20"
]
},
"vcvtps2ph xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x1D 128-bit"
],
"ExpectedArm64ASM": [
"fcvtn v16.4h, v17.4s"
]
},
"vcvtps2ph xmm0, ymm1, 00000000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"nearest rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff3fffff",
"msr fpcr, x0",
"fcvtnt z2.h, p7/m, z17.s",
"uzp2 z2.h, z2.h, z2.h",
"msr fpcr, x20",
"mov v16.16b, v2.16b"
]
},
"vcvtps2ph xmm0, ymm1, 00000001b": {
"ExpectedInstructionCount": 8,
"Comment": [
"-inf rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffffbfffff",
"orr x0, x0, #0x800000",
"msr fpcr, x0",
"fcvtnt z2.h, p7/m, z17.s",
"uzp2 z2.h, z2.h, z2.h",
"msr fpcr, x20",
"mov v16.16b, v2.16b"
]
},
"vcvtps2ph xmm0, ymm1, 00000010b": {
"ExpectedInstructionCount": 8,
"Comment": [
"+inf rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"and x0, x20, #0xffffffffff7fffff",
"orr x0, x0, #0x400000",
"msr fpcr, x0",
"fcvtnt z2.h, p7/m, z17.s",
"uzp2 z2.h, z2.h, z2.h",
"msr fpcr, x20",
"mov v16.16b, v2.16b"
]
},
"vcvtps2ph xmm0, ymm1, 00000011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"truncate rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"mrs x20, fpcr",
"orr x0, x20, #0xc00000",
"msr fpcr, x0",
"fcvtnt z2.h, p7/m, z17.s",
"uzp2 z2.h, z2.h, z2.h",
"msr fpcr, x20",
"mov v16.16b, v2.16b"
]
},
"vcvtps2ph xmm0, ymm1, 00000100b": {
"ExpectedInstructionCount": 3,
"Comment": [
"host mode rounding",
"Map 3 0b01 0x1D 256-bit"
],
"ExpectedArm64ASM": [
"fcvtnt z2.h, p7/m, z17.s",
"uzp2 z2.h, z2.h, z2.h",
"mov v16.16b, v2.16b"
]
},
"vpinsrb xmm0, xmm0, eax, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.b[0], w4",
"mov v16.16b, v2.16b"
]
},
"vpinsrb xmm0, xmm1, eax, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.b[0], w4"
]
},
"vpinsrb xmm0, xmm1, eax, 15": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.b[15], w4"
]
},
"vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b0000))": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x21 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[0], v18.s[0]"
]
},
"vinsertps xmm0, xmm1, xmm2, ((0b00 << 6) | (0b00 << 4) | (0b1111))": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x21 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vinsertps xmm0, xmm1, xmm2, ((0b11 << 6) | (0b11 << 4) | (0b0000))": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x21 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[3], v18.s[3]"
]
},
"vpinsrd xmm0, xmm0, eax, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.s[0], w4",
"mov v16.16b, v2.16b"
]
},
"vpinsrd xmm0, xmm1, eax, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[0], w4"
]
},
"vpinsrd xmm0, xmm1, eax, 3": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.s[3], w4"
]
},
"vpinsrq xmm0, xmm0, rax, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v2.16b, v16.16b",
"mov v2.d[0], x4",
"mov v16.16b, v2.16b"
]
},
"vpinsrq xmm0, xmm1, rax, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[0], x4"
]
},
"vpinsrq xmm0, xmm1, rax, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b",
"mov v16.d[1], x4"
]
},
"vinserti128 ymm0, ymm1, xmm2, 0": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x38 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.q, q18",
"mov z16.d, z17.d",
"mov z16.b, p6/m, z1.b"
]
},
"vinserti128 ymm0, ymm1, xmm2, 1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x38 256-bit"
],
"ExpectedArm64ASM": [
"mov z1.q, q18",
"mov z16.d, z17.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vextracti128 xmm0, ymm1, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x39 256-bit"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"vextracti128 xmm0, ymm1, 1": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x39 256-bit"
],
"ExpectedArm64ASM": [
"mov z2.q, z17.q[1]",
"mov v16.16b, v2.16b"
]
},
"vdpps xmm0, xmm1, xmm2, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdpps xmm0, xmm1, xmm2, 00001111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdpps xmm0, xmm1, xmm2, 11110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdpps xmm0, xmm1, xmm2, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"fmul v2.4s, v17.4s, v18.4s",
"faddv s2, p6, z2.s",
"dup v16.4s, v2.s[0]"
]
},
"vdpps ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdpps ymm0, ymm1, ymm2, 00001111b": {
"ExpectedInstructionCount": 109,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul z3.s, z17.s, z18.s",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s2",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z3.s, p0/m, z1.s",
"msr nzcv, x0",
"movprfx z0, z3",
"faddp z0.s, p7/m, z0.s, z2.s",
"uzp1 z3.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z3.d, p6, z3.d, z1.d",
"movprfx z0, z3",
"faddp z0.s, p7/m, z0.s, z2.s",
"uzp1 z3.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z3.d, p6, z3.d, z1.d",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vdpps ymm0, ymm1, ymm2, 11110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdpps ymm0, ymm1, ymm2, 11111111b": {
"ExpectedInstructionCount": 61,
"Comment": [
"Map 3 0b01 0x40 128-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul z3.s, z17.s, z18.s",
"movprfx z0, z3",
"faddp z0.s, p7/m, z0.s, z2.s",
"uzp1 z3.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z3.d, p6, z3.d, z1.d",
"movprfx z0, z3",
"faddp z0.s, p7/m, z0.s, z2.s",
"uzp1 z3.s, z0.s, z0.s",
"uzp2 z1.s, z0.s, z0.s",
"splice z3.d, p6, z3.d, z1.d",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-4",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-3",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #-1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #0",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #1",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #2",
"mov z2.s, p0/m, z1.s",
"msr nzcv, x0",
"mov z1.s, s3",
"mov z16.d, z2.d",
"mrs x0, nzcv",
"index z0.s, #-4, #1",
"cmpeq p0.s, p7/z, z0.s, #3",
"mov z16.s, p0/m, z1.s",
"msr nzcv, x0"
]
},
"vdppd xmm0, xmm1, xmm2, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdppd xmm0, xmm1, xmm2, 00001111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdppd xmm0, xmm1, xmm2, 11110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vdppd xmm0, xmm1, xmm2, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x41 128-bit"
],
"ExpectedArm64ASM": [
"fmul v2.2d, v17.2d, v18.2d",
"faddv d2, p6, z2.d",
"dup v16.2d, v2.d[0]"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 000b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[0]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 001b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[1]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 010b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[2]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 011b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[3]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 100b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[0]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 101b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[1]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 110b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[2]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw xmm0, xmm1, xmm2, 111b": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 3 0b01 0x42 128-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[3]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 000b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[0]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 001b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[1]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 010b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[2]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 011b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[3]",
"ext v3.16b, v17.16b, v17.16b, #0",
"ext v4.16b, v17.16b, v17.16b, #1",
"ext v5.16b, v17.16b, v17.16b, #2",
"ext v6.16b, v17.16b, v17.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 100b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[0]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 101b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[1]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 110b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[2]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vmpsadbw ymm0, ymm1, ymm2, 111b": {
"ExpectedInstructionCount": 34,
"Comment": [
"Map 3 0b01 0x42 256-bit"
],
"ExpectedArm64ASM": [
"dup v2.4s, v18.s[3]",
"ext v3.16b, v17.16b, v17.16b, #4",
"ext v4.16b, v17.16b, v17.16b, #5",
"ext v5.16b, v17.16b, v17.16b, #6",
"ext v6.16b, v17.16b, v17.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v2.8h, v4.8h, v2.8h",
"mov z3.q, z17.q[1]",
"mov z4.q, z18.q[1]",
"dup v4.4s, v4.s[0]",
"ext v5.16b, v3.16b, v3.16b, #0",
"ext v6.16b, v3.16b, v3.16b, #1",
"ext v7.16b, v3.16b, v3.16b, #2",
"ext v3.16b, v3.16b, v3.16b, #3",
"uabdl v5.8h, v5.8b, v4.8b",
"uabdl v6.8h, v6.8b, v4.8b",
"uabdl v7.8h, v7.8b, v4.8b",
"uabdl v3.8h, v3.8b, v4.8b",
"addp v4.8h, v5.8h, v7.8h",
"addp v3.8h, v6.8h, v3.8h",
"trn1 v5.4s, v4.4s, v3.4s",
"trn2 v3.4s, v4.4s, v3.4s",
"addp v3.8h, v5.8h, v3.8h",
"mov z1.q, q3",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 00000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"pmull v16.1q, v17.1d, v18.1d"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 00001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"dup v0.2d, v17.d[1]",
"pmull v16.1q, v0.1d, v18.1d"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 10000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"dup v0.2d, v18.d[1]",
"pmull v16.1q, v0.1d, v17.1d"
]
},
"vpclmulqdq xmm0, xmm1, xmm2, 10001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x44 128-bit"
],
"ExpectedArm64ASM": [
"pmull2 v16.1q, v17.2d, v18.2d"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 00000b": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x44 256-bit"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 00001b": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x44 256-bit"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 10000b": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x44 256-bit"
]
},
"vpclmulqdq ymm0, ymm1, ymm2, 10001b": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x44 256-bit"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00000011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00010011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00100011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110000b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110010b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00110011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z2.b, p6/m, z1.b",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00001000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00011000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00101000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 00111000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"not p0.b, p7/z, p6.b",
"mov z16.b, p0/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10001000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000000b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q17",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000001b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z17.q[1]",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000010b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, q18",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vperm2i128 ymm0, ymm1, ymm2, 10000011b": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 3 0b01 0x46 256-bit"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"mov z1.q, z18.q[1]",
"mov z16.d, z2.d",
"mov z16.b, p6/m, z1.b"
]
},
"vblendvps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x4a 128-bit"
],
"ExpectedArm64ASM": [
"sshr v2.4s, v19.4s, #31",
"mov v16.16b, v2.16b",
"bsl v16.16b, v18.16b, v17.16b"
]
},
"vblendvps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x4a 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z2, z19",
"asr z2.s, p7/m, z2.s, #31",
"movprfx z0, z18",
"bsl z0.d, z0.d, z17.d, z2.d",
"mov z16.d, z0.d"
]
},
"vblendvpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x4b 128-bit"
],
"ExpectedArm64ASM": [
"sshr v2.2d, v19.2d, #63",
"mov v16.16b, v2.16b",
"bsl v16.16b, v18.16b, v17.16b"
]
},
"vblendvpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x4b 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z2, z19",
"asr z2.d, p7/m, z2.d, #63",
"movprfx z0, z18",
"bsl z0.d, z0.d, z17.d, z2.d",
"mov z16.d, z0.d"
]
},
"vpblendvb xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 3 0b01 0x4c 128-bit"
],
"ExpectedArm64ASM": [
"sshr v2.16b, v19.16b, #7",
"mov v16.16b, v2.16b",
"bsl v16.16b, v18.16b, v17.16b"
]
},
"vpblendvb ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0x4c 256-bit"
],
"ExpectedArm64ASM": [
"movprfx z2, z19",
"asr z2.b, p7/m, z2.b, #7",
"movprfx z0, z18",
"bsl z0.d, z0.d, z17.d, z2.d",
"mov z16.d, z0.d"
]
},
"vfmaddsubps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5c 128-bit"
]
},
"vfmaddsubps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5c 256-bit"
]
},
"vfmaddsubpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5d 128-bit"
]
},
"vfmaddsubpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5d 256-bit"
]
},
"vfmsubaddps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5e 128-bit"
]
},
"vfmsubaddps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5e 256-bit"
]
},
"vfmsubaddpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5f 128-bit"
]
},
"vfmsubaddpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x5f 256-bit"
]
},
"vfmaddps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x68 128-bit"
]
},
"vfmaddps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x68 256-bit"
]
},
"vfmaddpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x69 128-bit"
]
},
"vfmaddpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x69 256-bit"
]
},
"vfmaddss xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6a 128-bit"
]
},
"vfmaddsd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6b 128-bit"
]
},
"vfmsubps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6c 128-bit"
]
},
"vfmsubps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6c 256-bit"
]
},
"vfmsubpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6d 128-bit"
]
},
"vfmsubpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6d 256-bit"
]
},
"vfmsubss xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6e 128-bit"
]
},
"vfmsubsd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x6f 128-bit"
]
},
"vfnmaddps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x78 128-bit"
]
},
"vfnmaddpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x78 256-bit"
]
},
"vfnmaddss xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x79 128-bit"
]
},
"vfnmaddsd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7a 128-bit"
]
},
"vfnmsubps xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7c 128-bit"
]
},
"vfnmsubps ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7c 256-bit"
]
},
"vfnmsubpd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7d 128-bit"
]
},
"vfnmsubpd ymm0, ymm1, ymm2, ymm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7d 256-bit"
]
},
"vfnmsubss xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7e 128-bit"
]
},
"vfnmsubsd xmm0, xmm1, xmm2, xmm3": {
"ExpectedInstructionCount": -1,
"Skip": "Yes",
"Comment": [
"Map 3 0b01 0x7f 128-bit"
]
},
"vaeskeygenassist xmm0, xmm1, 0": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
"tbl v16.16b, {v16.16b}, v2.16b"
]
},
"vaeskeygenassist xmm0, xmm1, 0xFF": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 3 0b01 0xdf 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2528]",
"movi v3.2d, #0x0",
"mov v16.16b, v17.16b",
"unimplemented (Unimplemented)",
"tbl v16.16b, {v16.16b}, v2.16b",
"mov x0, #0xff00000000",
"dup v1.2d, x0",
"eor v16.16b, v16.16b, v1.16b"
]
},
"rorx eax, ebx, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"mov w4, w7"
]
},
"rorx eax, eax, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"mov w4, w4"
]
},
"rorx eax, ebx, 31": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"ror w4, w7, #31"
]
},
"rorx eax, ebx, 32": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"mov w4, w7"
]
},
"rorx eax, eax, 32": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 32-bit"
],
"ExpectedArm64ASM": [
"mov w4, w4"
]
},
"rorx rax, rbx, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": [
"mov x4, x7"
]
},
"rorx rax, rax, 0": {
"ExpectedInstructionCount": 0,
"Comment": [
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": []
},
"rorx rax, rbx, 63": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": [
"ror x4, x7, #63"
]
},
"rorx rax, rbx, 64": {
"ExpectedInstructionCount": 1,
"Comment": [
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": [
"mov x4, x7"
]
},
"rorx rax, rax, 64": {
"ExpectedInstructionCount": 0,
"Comment": [
"Map 3 0b11 0xf0 64-bit"
],
"ExpectedArm64ASM": []
}
}
}
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