FEX/unittests/InstructionCountCI/Secondary_32Bit.json
Alyssa Rosenzweig f5bc06476a InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-08-14 09:37:06 -04:00

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{
"Features": {
"Bitness": 32,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP"
]
},
"Instructions": {
"push fs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa0",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #938]",
"str w20, [x8, #-4]!"
]
},
"pop fs": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xa1",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #938]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #1168]",
"str w20, [x28, #968]"
]
},
"push gs": {
"ExpectedInstructionCount": 2,
"Comment": "0x0f 0xa8",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #936]",
"str w20, [x8, #-4]!"
]
},
"pop gs": {
"ExpectedInstructionCount": 6,
"Comment": "0x0f 0xa9",
"ExpectedArm64ASM": [
"ldr w20, [x8], #4",
"strh w20, [x28, #936]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #1168]",
"str w20, [x28, #960]"
]
}
}
}