mirror of
https://github.com/FEX-Emu/FEX.git
synced 2025-01-05 21:09:56 +00:00
27c8bf3021
(except for when we explicitly enable AFP). Since AFP gets saved/restored, we get `msr fpcr` garbage in random instructions when AFP is enabled. Explicitly disable everywhere since it's not worth our time to triage which files might hit that path. Fixes instcountci on AFP-supporting hosts now that we have AFP enabled. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
93 lines
2.1 KiB
JSON
93 lines
2.1 KiB
JSON
{
|
|
"Features": {
|
|
"Bitness": 64,
|
|
"EnabledHostFeatures": [
|
|
"SVE128"
|
|
],
|
|
"DisabledHostFeatures": [
|
|
"SVE256",
|
|
"AFP"
|
|
]
|
|
},
|
|
"Instructions": {
|
|
"psrlw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xd1",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"lsr z16.h, p6/m, z16.h, z0.d"
|
|
]
|
|
},
|
|
"psrld xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xd2",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"lsr z16.s, p6/m, z16.s, z0.d"
|
|
]
|
|
},
|
|
"psrlq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xd3",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"lsr z16.d, p6/m, z16.d, z0.d"
|
|
]
|
|
},
|
|
"psraw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xe1",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"asr z16.h, p6/m, z16.h, z0.d"
|
|
]
|
|
},
|
|
"psrad xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xe2",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"asr z16.s, p6/m, z16.s, z0.d"
|
|
]
|
|
},
|
|
"pmulhuw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe4",
|
|
"ExpectedArm64ASM": [
|
|
"umulh z16.h, z16.h, z17.h"
|
|
]
|
|
},
|
|
"pmulhw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe5",
|
|
"ExpectedArm64ASM": [
|
|
"smulh z16.h, z16.h, z17.h"
|
|
]
|
|
},
|
|
"psllw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xf1",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"lsl z16.h, p6/m, z16.h, z0.d"
|
|
]
|
|
},
|
|
"pslld xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xf2",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"lsl z16.s, p6/m, z16.s, z0.d"
|
|
]
|
|
},
|
|
"psllq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xf3",
|
|
"ExpectedArm64ASM": [
|
|
"mov z0.d, d17",
|
|
"lsl z16.d, p6/m, z16.d, z0.d"
|
|
]
|
|
}
|
|
}
|
|
}
|