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FEX/unittests/InstructionCountCI/H0F3A.json
Ryan Houdek 175d407c9f InstCountCI: Update for segment changes
2023-12-21 01:54:19 -08:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP",
"CRYPTO"
]
},
"Comment": [
"SSE4.2 string instructions are skipped here.",
"Entirely because they are nightmare implementations of instructions."
],
"Instructions": {
"palignr mm0, mm1, 0": {
"ExpectedInstructionCount": 2,
"Comment": [
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"str d2, [x28, #768]"
]
},
"palignr mm0, mm1, 1": {
"ExpectedInstructionCount": 4,
"Comment": [
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ldr d2, [x28, #784]",
"ldr d3, [x28, #768]",
"ext v2.8b, v2.8b, v3.8b, #1",
"str d2, [x28, #768]"
]
},
"palignr mm0, mm1, 255": {
"ExpectedInstructionCount": 2,
"Comment": [
"NP 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"str d2, [x28, #768]"
]
},
"roundps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Nearest rounding",
"0x66 0x0f 0x3a 0x08"
],
"ExpectedArm64ASM": [
"frintn v16.4s, v17.4s"
]
},
"roundps xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"-inf rounding",
"0x66 0x0f 0x3a 0x08"
],
"ExpectedArm64ASM": [
"frintm v16.4s, v17.4s"
]
},
"roundps xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"+inf rounding",
"0x66 0x0f 0x3a 0x08"
],
"ExpectedArm64ASM": [
"frintp v16.4s, v17.4s"
]
},
"roundps xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"truncate rounding",
"0x66 0x0f 0x3a 0x08"
],
"ExpectedArm64ASM": [
"frintz v16.4s, v17.4s"
]
},
"roundps xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host rounding mode rounding",
"0x66 0x0f 0x3a 0x08"
],
"ExpectedArm64ASM": [
"frinti v16.4s, v17.4s"
]
},
"roundpd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"Nearest rounding",
"0x66 0x0f 0x3a 0x09"
],
"ExpectedArm64ASM": [
"frintn v16.2d, v17.2d"
]
},
"roundpd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"-inf rounding",
"0x66 0x0f 0x3a 0x09"
],
"ExpectedArm64ASM": [
"frintm v16.2d, v17.2d"
]
},
"roundpd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"+inf rounding",
"0x66 0x0f 0x3a 0x09"
],
"ExpectedArm64ASM": [
"frintp v16.2d, v17.2d"
]
},
"roundpd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"truncate rounding",
"0x66 0x0f 0x3a 0x09"
],
"ExpectedArm64ASM": [
"frintz v16.2d, v17.2d"
]
},
"roundpd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"host rounding mode rounding",
"0x66 0x0f 0x3a 0x09"
],
"ExpectedArm64ASM": [
"frinti v16.2d, v17.2d"
]
},
"roundss xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Nearest rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintn s0, s17",
"mov v16.s[0], v0.s[0]"
]
},
"roundss xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"-inf rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintm s0, s17",
"mov v16.s[0], v0.s[0]"
]
},
"roundss xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"+inf rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintp s0, s17",
"mov v16.s[0], v0.s[0]"
]
},
"roundss xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"truncate rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frintz s0, s17",
"mov v16.s[0], v0.s[0]"
]
},
"roundss xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"host rounding mode rounding",
"0x66 0x0f 0x3a 0x0a"
],
"ExpectedArm64ASM": [
"frinti s0, s17",
"mov v16.s[0], v0.s[0]"
]
},
"roundsd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 2,
"Comment": [
"Nearest rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintn d0, d17",
"mov v16.d[0], v0.d[0]"
]
},
"roundsd xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"-inf rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintm d0, d17",
"mov v16.d[0], v0.d[0]"
]
},
"roundsd xmm0, xmm1, 00000010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"+inf rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintp d0, d17",
"mov v16.d[0], v0.d[0]"
]
},
"roundsd xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"truncate rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frintz d0, d17",
"mov v16.d[0], v0.d[0]"
]
},
"roundsd xmm0, xmm1, 00000100b": {
"ExpectedInstructionCount": 2,
"Comment": [
"host rounding mode rounding",
"0x66 0x0f 0x3a 0x0b"
],
"ExpectedArm64ASM": [
"frinti d0, d17",
"mov v16.d[0], v0.d[0]"
]
},
"blendps xmm0, xmm1, 0000b": {
"ExpectedInstructionCount": 0,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": []
},
"blendps xmm0, xmm1, 0001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.s[0], v17.s[0]"
]
},
"blendps xmm0, xmm1, 0010b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.s[1], v17.s[1]"
]
},
"blendps xmm0, xmm1, 0011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.d[0], v17.d[0]"
]
},
"blendps xmm0, xmm1, 0100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.s[2], v17.s[2]"
]
},
"blendps xmm0, xmm1, 0101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v17.4s",
"trn2 v16.4s, v2.4s, v16.4s"
]
},
"blendps xmm0, xmm1, 0110b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2224]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"blendps xmm0, xmm1, 0111b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2240]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"blendps xmm0, xmm1, 1000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.s[3], v17.s[3]"
]
},
"blendps xmm0, xmm1, 1001b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2256]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"blendps xmm0, xmm1, 1010b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"rev64 v2.4s, v16.4s",
"trn2 v16.4s, v2.4s, v17.4s"
]
},
"blendps xmm0, xmm1, 1011b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2272]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"blendps xmm0, xmm1, 1100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.d[1], v17.d[1]"
]
},
"blendps xmm0, xmm1, 1101b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2288]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"blendps xmm0, xmm1, 1110b": {
"ExpectedInstructionCount": 2,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #2304]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"blendps xmm0, xmm1, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0c"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"blendpd xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 0,
"Comment": [
"0x66 0x0f 0x3a 0x0d"
],
"ExpectedArm64ASM": []
},
"blendpd xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0d"
],
"ExpectedArm64ASM": [
"mov v16.d[0], v17.d[0]"
]
},
"blendpd xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0d"
],
"ExpectedArm64ASM": [
"mov v16.d[1], v17.d[1]"
]
},
"blendpd xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0d"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"pblendw xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 0,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": []
},
"pblendw xmm0, xmm1, 00000001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.h[0], v17.h[0]"
]
},
"pblendw xmm0, xmm1, 11010111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"ldr x0, [x28, #1848]",
"ldr q2, [x0, #3440]",
"tbx v16.16b, {v17.16b}, v2.16b"
]
},
"pblendw xmm0, xmm1, 00000011b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.s[0], v17.s[0]"
]
},
"pblendw xmm0, xmm1, 00001100b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.s[1], v17.s[1]"
]
},
"pblendw xmm0, xmm1, 00110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.s[2], v17.s[2]"
]
},
"pblendw xmm0, xmm1, 11000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.s[3], v17.s[3]"
]
},
"pblendw xmm0, xmm1, 00001111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.d[0], v17.d[0]"
]
},
"pblendw xmm0, xmm1, 11110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.d[1], v17.d[1]"
]
},
"pblendw xmm0, xmm1, 11111111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0e"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"palignr xmm0, xmm1, 0": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"mov v16.16b, v17.16b"
]
},
"palignr xmm0, xmm1, 1": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"ext v16.16b, v17.16b, v16.16b, #1"
]
},
"palignr xmm0, xmm1, 255": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x0f"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"pextrb eax, xmm0, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x14"
],
"ExpectedArm64ASM": [
"umov w4, v16.b[0]"
]
},
"pextrb eax, xmm0, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x14"
],
"ExpectedArm64ASM": [
"umov w4, v16.b[15]"
]
},
"pextrw eax, xmm0, 000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x15"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[0]"
]
},
"pextrw eax, xmm0, 111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x15"
],
"ExpectedArm64ASM": [
"umov w4, v16.h[7]"
]
},
"pextrd eax, xmm0, 00b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[0]"
]
},
"pextrd eax, xmm0, 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[3]"
]
},
"pextrq rax, xmm0, 0b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"mov x4, v16.d[0]"
]
},
"pextrq rax, xmm0, 1b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"mov x4, v16.d[1]"
]
},
"pextrb [rax], xmm0, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x14"
],
"ExpectedArm64ASM": [
"st1 {v16.b}[0], [x4]"
]
},
"pextrb [rax], xmm0, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x14"
],
"ExpectedArm64ASM": [
"st1 {v16.b}[15], [x4]"
]
},
"pextrw [rax], xmm0, 000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x15"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[0], [x4]"
]
},
"pextrw [rax], xmm0, 111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x15"
],
"ExpectedArm64ASM": [
"st1 {v16.h}[7], [x4]"
]
},
"pextrd [rax], xmm0, 00b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"st1 {v16.s}[0], [x4]"
]
},
"pextrd [rax], xmm0, 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"st1 {v16.s}[3], [x4]"
]
},
"pextrq [rax], xmm0, 0b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"st1 {v16.d}[0], [x4]"
]
},
"pextrq [rax], xmm0, 1b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x16"
],
"ExpectedArm64ASM": [
"st1 {v16.d}[1], [x4]"
]
},
"extractps eax, xmm0, 00b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x17"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[0]"
]
},
"extractps eax, xmm0, 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x17"
],
"ExpectedArm64ASM": [
"mov w4, v16.s[3]"
]
},
"pinsrb xmm0, eax, 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"mov v16.b[0], w4"
]
},
"pinsrb xmm0, eax, 0001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"mov v16.b[1], w4"
]
},
"pinsrb xmm0, eax, 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"mov v16.b[15], w4"
]
},
"pinsrb xmm0, [rax], 0000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"ld1 {v16.b}[0], [x4]"
]
},
"pinsrb xmm0, [rax], 0001b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"ld1 {v16.b}[1], [x4]"
]
},
"pinsrb xmm0, [rax], 1111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"ld1 {v16.b}[15], [x4]"
]
},
"insertps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x21"
],
"ExpectedArm64ASM": [
"mov v16.s[0], v17.s[0]"
]
},
"insertps xmm0, xmm1, 00001111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x21"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"insertps xmm0, xmm1, 00010000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x21"
],
"ExpectedArm64ASM": [
"mov v16.s[1], v17.s[0]"
]
},
"pinsrd xmm0, eax, 00b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"mov v16.s[0], w4"
]
},
"pinsrd xmm0, eax, 01b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"mov v16.s[1], w4"
]
},
"pinsrd xmm0, eax, 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"mov v16.s[3], w4"
]
},
"pinsrq xmm0, rax, 0b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"mov v16.d[0], x4"
]
},
"pinsrq xmm0, rax, 1b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"mov v16.d[1], x4"
]
},
"pinsrd xmm0, [rax], 00b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.s}[0], [x4]"
]
},
"pinsrd xmm0, [rax], 01b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.s}[1], [x4]"
]
},
"pinsrd xmm0, [rax], 11b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.s}[3], [x4]"
]
},
"pinsrq xmm0, [rax], 0b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.d}[0], [x4]"
]
},
"pinsrq xmm0, [rax], 1b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.d}[1], [x4]"
]
},
"dpps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"dpps xmm0, xmm1, 00001111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"dpps xmm0, xmm1, 11110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"dpps xmm0, xmm1, 11110001b": {
"ExpectedInstructionCount": 5,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"zip1 v16.4s, v3.4s, v2.4s"
]
},
"dpps xmm0, xmm1, 11110010b": {
"ExpectedInstructionCount": 5,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"zip1 v16.2s, v2.2s, v3.2s"
]
},
"dpps xmm0, xmm1, 11110011b": {
"ExpectedInstructionCount": 4,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"fmul v2.4s, v16.4s, v17.4s",
"faddp v2.4s, v2.4s, v2.4s",
"faddp s2, v2.2s",
"dup v16.2s, v2.s[0]"
]
},
"dpps xmm0, xmm1, 11110100b": {
"ExpectedInstructionCount": 5,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"dpps xmm0, xmm1, 11110101b": {
"ExpectedInstructionCount": 4,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"fmul v2.4s, v16.4s, v17.4s",
"faddp v2.4s, v2.4s, v2.4s",
"faddp s2, v2.2s",
"zip1 v16.2d, v2.2d, v2.2d"
]
},
"dpps xmm0, xmm1, 11110110b": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"mov v2.s[1], v3.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[2], v3.s[0]"
]
},
"dpps xmm0, xmm1, 11110111b": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"dup v3.4s, v3.s[0]",
"mov v16.16b, v3.16b",
"mov v16.s[3], v2.s[0]"
]
},
"dpps xmm0, xmm1, 11111000b": {
"ExpectedInstructionCount": 5,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"ext v16.16b, v2.16b, v3.16b, #4"
]
},
"dpps xmm0, xmm1, 11111001b": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"mov v2.s[0], v3.s[0]",
"mov v16.16b, v2.16b",
"mov v16.s[3], v3.s[0]"
]
},
"dpps xmm0, xmm1, 11111010b": {
"ExpectedInstructionCount": 6,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"dup v3.4s, v3.s[0]",
"zip1 v16.4s, v2.4s, v3.4s"
]
},
"dpps xmm0, xmm1, 11111011b": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"dup v3.4s, v3.s[0]",
"mov v16.16b, v3.16b",
"mov v16.s[2], v2.s[0]"
]
},
"dpps xmm0, xmm1, 11111100b": {
"ExpectedInstructionCount": 6,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"dup v3.4s, v3.s[0]",
"zip1 v16.2d, v2.2d, v3.2d"
]
},
"dpps xmm0, xmm1, 11111101b": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"dup v3.4s, v3.s[0]",
"mov v16.16b, v3.16b",
"mov v16.s[1], v2.s[0]"
]
},
"dpps xmm0, xmm1, 11111110b": {
"ExpectedInstructionCount": 7,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"fmul v3.4s, v16.4s, v17.4s",
"faddp v3.4s, v3.4s, v3.4s",
"faddp s3, v3.2s",
"dup v3.4s, v3.s[0]",
"mov v16.16b, v3.16b",
"mov v16.s[0], v2.s[0]"
]
},
"dpps xmm0, xmm1, 11111111b": {
"ExpectedInstructionCount": 4,
"Comment": [
"0x66 0x0f 0x3a 0x40"
],
"ExpectedArm64ASM": [
"fmul v2.4s, v16.4s, v17.4s",
"faddp v2.4s, v2.4s, v2.4s",
"faddp s2, v2.2s",
"dup v16.4s, v2.s[0]"
]
},
"dppd xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x41"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"dppd xmm0, xmm1, 00001111b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x41"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"dppd xmm0, xmm1, 11110000b": {
"ExpectedInstructionCount": 1,
"Comment": [
"0x66 0x0f 0x3a 0x41"
],
"ExpectedArm64ASM": [
"movi v16.2d, #0x0"
]
},
"dppd xmm0, xmm1, 11111111b": {
"ExpectedInstructionCount": 3,
"Comment": [
"0x66 0x0f 0x3a 0x41"
],
"ExpectedArm64ASM": [
"fmul v2.2d, v16.2d, v17.2d",
"faddp d2, v2.2d",
"dup v16.2d, v2.d[0]"
]
},
"mpsadbw xmm0, xmm1, 000b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[0]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 001b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[1]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 010b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[2]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 011b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[3]",
"ext v3.16b, v16.16b, v16.16b, #0",
"ext v4.16b, v16.16b, v16.16b, #1",
"ext v5.16b, v16.16b, v16.16b, #2",
"ext v6.16b, v16.16b, v16.16b, #3",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 100b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[0]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 101b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[1]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 110b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[2]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"mpsadbw xmm0, xmm1, 111b": {
"ExpectedInstructionCount": 14,
"Comment": [
"0x66 0x0f 0x3a 0x42"
],
"ExpectedArm64ASM": [
"dup v2.4s, v17.s[3]",
"ext v3.16b, v16.16b, v16.16b, #4",
"ext v4.16b, v16.16b, v16.16b, #5",
"ext v5.16b, v16.16b, v16.16b, #6",
"ext v6.16b, v16.16b, v16.16b, #7",
"uabdl v3.8h, v3.8b, v2.8b",
"uabdl v4.8h, v4.8b, v2.8b",
"uabdl v5.8h, v5.8b, v2.8b",
"uabdl v2.8h, v6.8b, v2.8b",
"addp v3.8h, v3.8h, v5.8h",
"addp v2.8h, v4.8h, v2.8h",
"trn1 v4.4s, v3.4s, v2.4s",
"trn2 v2.4s, v3.4s, v2.4s",
"addp v16.8h, v4.8h, v2.8h"
]
},
"sha1rnds4 xmm0, xmm1, 00b": {
"ExpectedInstructionCount": 65,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x60 (96)",
"mov w20, #0x7999",
"movk w20, #0x5a82, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"str w21, [sp, #64]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"str w21, [sp]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"and w25, w22, w23",
"bic w30, w24, w22",
"eor w25, w25, w30",
"ror w30, w21, #27",
"add w25, w25, w30",
"add w20, w25, w20",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w20, w20, w25",
"ror w22, w22, #2",
"and w25, w21, w22",
"bic w30, w23, w21",
"eor w25, w25, w30",
"ror w30, w20, #27",
"add w25, w25, w30",
"ldr w30, [sp, #64]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w24, w24, w25",
"ror w21, w21, #2",
"and w25, w20, w21",
"bic w30, w22, w20",
"eor w25, w25, w30",
"ror w30, w24, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w23, w25, w23",
"mov w25, #0x7999",
"movk w25, #0x5a82, lsl #16",
"add w23, w23, w25",
"ror w20, w20, #2",
"and w30, w24, w20",
"bic w21, w21, w24",
"eor w21, w30, w21",
"ror w30, w23, #27",
"add w21, w21, w30",
"ldr w30, [sp]",
"add w21, w21, w30",
"add w21, w21, w22",
"add w21, w21, w25",
"ror w22, w24, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w21",
"mov v2.s[2], w23",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 01b": {
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x60 (96)",
"mov w20, #0xeba1",
"movk w20, #0x6ed9, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"str w22, [sp, #32]",
"mov w22, v17.s[0]",
"str w22, [sp]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w25, v16.s[0]",
"eor w30, w23, w24",
"eor w30, w30, w25",
"str w25, [sp, #64]",
"ror w25, w22, #27",
"add w25, w30, w25",
"add w20, w25, w20",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w20, w20, w25",
"ror w23, w23, #2",
"eor w25, w22, w23",
"eor w25, w25, w24",
"ror w30, w20, #27",
"add w25, w25, w30",
"add w21, w25, w21",
"ldr w25, [sp, #64]",
"add w21, w21, w25",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w21, w21, w25",
"ror w22, w22, #2",
"eor w25, w20, w22",
"eor w25, w25, w23",
"ror w30, w21, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xeba1",
"movk w25, #0x6ed9, lsl #16",
"add w24, w24, w25",
"ror w20, w20, #2",
"eor w30, w21, w20",
"eor w22, w30, w22",
"ror w30, w24, #27",
"add w22, w22, w30",
"ldr w30, [sp]",
"add w22, w22, w30",
"add w22, w22, w23",
"add w22, w22, w25",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 10b": {
"ExpectedInstructionCount": 75,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x60 (96)",
"mov w20, #0xbcdc",
"movk w20, #0x8f1b, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"str w21, [sp, #64]",
"mov w21, v17.s[1]",
"str w21, [sp, #32]",
"mov w21, v17.s[0]",
"str w21, [sp]",
"mov w21, v16.s[3]",
"mov w22, v16.s[2]",
"mov w23, v16.s[1]",
"mov w24, v16.s[0]",
"and w25, w22, w23",
"and w30, w22, w24",
"eor w25, w25, w30",
"and w30, w23, w24",
"eor w25, w25, w30",
"ror w30, w21, #27",
"add w25, w25, w30",
"add w20, w25, w20",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w20, w20, w25",
"ror w22, w22, #2",
"and w25, w21, w22",
"and w30, w21, w23",
"eor w25, w25, w30",
"and w30, w22, w23",
"eor w25, w25, w30",
"ror w30, w20, #27",
"add w25, w25, w30",
"ldr w30, [sp, #64]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w24, w24, w25",
"ror w21, w21, #2",
"and w25, w20, w21",
"and w30, w20, w22",
"eor w25, w25, w30",
"and w30, w21, w22",
"eor w25, w25, w30",
"ror w30, w24, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w23, w25, w23",
"mov w25, #0xbcdc",
"movk w25, #0x8f1b, lsl #16",
"add w23, w23, w25",
"ror w20, w20, #2",
"and w25, w24, w20",
"and w30, w24, w21",
"eor w25, w25, w30",
"and w21, w20, w21",
"eor w21, w25, w21",
"ror w25, w23, #27",
"add w21, w21, w25",
"ldr w25, [sp]",
"add w21, w21, w25",
"add w21, w21, w22",
"mov w22, #0xbcdc",
"movk w22, #0x8f1b, lsl #16",
"add w21, w21, w22",
"ror w22, w24, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w21",
"mov v2.s[2], w23",
"mov v2.s[1], w22",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x60 (96)"
]
},
"sha1rnds4 xmm0, xmm1, 11b": {
"ExpectedInstructionCount": 61,
"Comment": [
"0x66 0x0f 0x3a 0xcc"
],
"ExpectedArm64ASM": [
"sub sp, sp, #0x60 (96)",
"mov w20, #0xc1d6",
"movk w20, #0xca62, lsl #16",
"mov w20, v17.s[3]",
"mov w21, v17.s[2]",
"mov w22, v17.s[1]",
"str w22, [sp, #32]",
"mov w22, v17.s[0]",
"str w22, [sp]",
"mov w22, v16.s[3]",
"mov w23, v16.s[2]",
"mov w24, v16.s[1]",
"mov w25, v16.s[0]",
"eor w30, w23, w24",
"eor w30, w30, w25",
"str w25, [sp, #64]",
"ror w25, w22, #27",
"add w25, w30, w25",
"add w20, w25, w20",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w20, w20, w25",
"ror w23, w23, #2",
"eor w25, w22, w23",
"eor w25, w25, w24",
"ror w30, w20, #27",
"add w25, w25, w30",
"add w21, w25, w21",
"ldr w25, [sp, #64]",
"add w21, w21, w25",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w21, w21, w25",
"ror w22, w22, #2",
"eor w25, w20, w22",
"eor w25, w25, w23",
"ror w30, w21, #27",
"add w25, w25, w30",
"ldr w30, [sp, #32]",
"add w25, w25, w30",
"add w24, w25, w24",
"mov w25, #0xc1d6",
"movk w25, #0xca62, lsl #16",
"add w24, w24, w25",
"ror w20, w20, #2",
"eor w30, w21, w20",
"eor w22, w30, w22",
"ror w30, w24, #27",
"add w22, w22, w30",
"ldr w30, [sp]",
"add w22, w22, w30",
"add w22, w22, w23",
"add w22, w22, w25",
"ror w21, w21, #2",
"mov v2.16b, v16.16b",
"mov v2.s[3], w22",
"mov v2.s[2], w24",
"mov v2.s[1], w21",
"mov v16.16b, v2.16b",
"mov v16.s[0], w20",
"add sp, sp, #0x60 (96)"
]
}
}
}
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