FEX/unittests
Ryan Houdek fb7167c2d2
CodeEmitter: Fixes vector {ldr,str}{b,h} with reg-reg source
We had failed to enable these implementations for the
`ExtendedMemOperand` helpers. We had already implemented the non-helper
forms, which are already tested in CI. These helpers just weren't
updated?

Noticed this when running libaom's SSE4.1 tests, where it managed to
execute a pmovzxbq instruction with reg+reg memory source and was
breaking the test results.

There are /very/ few vector register operations that access only 8-bit
or 16-bit in vectors so this flew under the radar for quite a while.

Fixes their unit tests.

Also adds a unittest using sse4.1 pmovzxbq to ensure we support the
reg+reg case, and also a few other instructions to test 8-bit and 16-bit
vector loads and stores.
2024-07-01 17:03:47 -07:00
..
2024-04-12 16:26:02 +02:00
2024-07-01 13:54:11 -07:00
2024-04-15 09:40:00 +02:00
2020-08-21 01:29:37 +12:00
2021-03-30 12:21:18 +03:00

FEX Unit tests

FEX has its own test suite for x86-64 emulation, and we also use gcc's target tests, posixtest, and gvisor's tests. We use a combination of CMake/CTest and python runner scripts.

We also regularly run and pass qemu's and valgrind's tests for validation, but those aren't in CI right now.

x86/64 testing

  • A lot of handwritten assembly unit tests in 32Bit_ASM and ASM folders, run via our TestHarnessHelper
  • A few handwritten IR tests in IR, run via our IRLoader
  • gcc-target-tests-32 and gcc-target-tests-64, run via FEXLoader. The tests binaries are in External/fex-gcc-target-tests-bins

Syscall testing