mirror of
https://github.com/FEX-Emu/FEX.git
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110 lines
1.9 KiB
NASM
110 lines
1.9 KiB
NASM
%ifdef CONFIG
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{
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"RegData": {
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"R8": "0x246",
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"R9": "0x246",
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"R10": "0x246",
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"R11": "0x246",
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"R12": "0x246",
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"R13": "0x246",
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"R14": "0x246",
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"R15": "0x246"
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}
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}
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%endif
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; FEX-Emu had a bug where 8-bit and 16-bit shifts with large offsets would calculate flags incorrectly.
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mov rsp, 0xe000_1000
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mov rax, 0x8234fdb482345679
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; Large shift that is larger than the element size but smaller than mask limit of 0x1F
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mov rcx, 0x5152535455565714
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jmp .test
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.test:
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; Ensure that 16-bit shift updates flags correctly.
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shl ax, cl
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pushfq
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pop r15
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; Clear OF and AF since those are undefined
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and r15, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test2
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.test2:
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sar ax, cl
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pushfq
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pop r14
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; Clear OF and AF since those are undefined
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and r14, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test3
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.test3:
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shl ax, 0x14
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pushfq
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pop r13
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; Clear OF and AF since those are undefined
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and r13, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test4
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.test4:
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sar ax, 0x14
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pushfq
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pop r12
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; Clear OF and AF since those are undefined
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and r12, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test5
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.test5:
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; Ensure that 8-bit shift updates flags correctly.
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shl al, cl
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pushfq
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pop r11
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; Clear OF and AF since those are undefined
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and r11, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test6
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.test6:
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sar al, cl
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pushfq
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pop r10
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; Clear OF and AF since those are undefined
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and r10, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test7
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.test7:
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shl al, 0x14
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pushfq
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pop r9
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; Clear OF and AF since those are undefined
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and r9, ~((1 << 11) | (1 << 4))
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; Set up the next test.
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mov rax, 0x8234fdb482345679
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jmp .test8
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.test8:
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sar al, 0x14
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pushfq
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pop r8
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; Clear OF and AF since those are undefined
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and r8, ~((1 << 11) | (1 << 4))
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hlt
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