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mips: remote unwind support
libunwind already had support for local unwind on a MIPS. This patch makes support for remote unwinding on a MIPS. I should add a few words to the changes to _UPT_access_mem.c: On MIPS, an unw_word_t is defined as a 64-bit integer whether it's compiled for a 32- or a 64-bit MIPS. When doing remote unwinding using the default _UPT_accessors, dwarf_readu8() therefore expects _UPT_access_mem() to return a 64-bit integer. However, if compiled on a 32-bit MIPS, only 32 bits are valid upon return from _UPT_access_mem(). The patch detects this and will in this case perform two calls to ptrace(PTRACE_POKE/PEEK_DATA) and organize the return value according to endianness.
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@ -30,7 +30,7 @@ extern "C" {
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#endif
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#include <inttypes.h>
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#include <ucontext.h>
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#include <sys/ucontext.h>
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#ifdef mips
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# undef mips
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@ -103,7 +103,7 @@ typedef enum
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previous frame. */
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UNW_MIPS_CFA,
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UNW_TDEP_LAST_REG = UNW_MIPS_R31,
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UNW_TDEP_LAST_REG = UNW_MIPS_PC,
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UNW_TDEP_IP = UNW_MIPS_R31,
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UNW_TDEP_SP = UNW_MIPS_R29,
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@ -32,33 +32,66 @@ _UPT_access_mem (unw_addr_space_t as, unw_word_t addr, unw_word_t *val,
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int write, void *arg)
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{
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struct UPT_info *ui = arg;
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int i, end;
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unw_word_t tmp_val;
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if (!ui)
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return -UNW_EINVAL;
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pid_t pid = ui->pid;
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errno = 0;
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if (write)
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{
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Debug (16, "mem[%lx] <- %lx\n", (long) addr, (long) *val);
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#ifdef HAVE_TTRACE
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# warning No support for ttrace() yet.
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#else
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ptrace (PTRACE_POKEDATA, pid, addr, *val);
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if (errno)
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return -UNW_EINVAL;
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#endif
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}
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// Some 32-bit archs have to define a 64-bit unw_word_t.
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// Callers of this function therefore expect a 64-bit
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// return value, but ptrace only returns a 32-bit value
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// in such cases.
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if (sizeof(long) == 4 && sizeof(unw_word_t) == 8)
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end = 2;
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else
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end = 1;
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for (i = 0; i < end; i++)
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{
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#ifdef HAVE_TTRACE
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# warning No support for ttrace() yet.
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unw_word_t tmp_addr = i == 0 ? addr : addr + 4;
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errno = 0;
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if (write)
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{
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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tmp_val = i == 0 ? *val : *val >> 32;
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#else
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*val = ptrace (PTRACE_PEEKDATA, pid, addr, 0);
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if (errno)
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return -UNW_EINVAL;
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tmp_val = i == 0 && end == 2 ? *val >> 32 : *val;
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#endif
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Debug (16, "mem[%lx] -> %lx\n", (long) addr, (long) *val);
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Debug (16, "mem[%lx] <- %lx\n", (long) tmp_addr, (long) tmp_val);
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#ifdef HAVE_TTRACE
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# warning No support for ttrace() yet.
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#else
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ptrace (PTRACE_POKEDATA, pid, tmp_addr, tmp_val);
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if (errno)
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return -UNW_EINVAL;
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#endif
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}
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else
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{
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#ifdef HAVE_TTRACE
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# warning No support for ttrace() yet.
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#else
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tmp_val = (unsigned long) ptrace (PTRACE_PEEKDATA, pid, tmp_addr, 0);
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if (i == 0)
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*val = 0;
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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*val |= tmp_val << (i * 32);
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#else
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*val |= i == 0 && end == 2 ? tmp_val << 32 : tmp_val;
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#endif
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if (errno)
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return -UNW_EINVAL;
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#endif
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Debug (16, "mem[%lx] -> %lx\n", (long) tmp_addr, (long) tmp_val);
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}
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}
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return 0;
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}
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@ -501,6 +501,39 @@ const int _UPT_reg_offset[UNW_REG_LAST + 1] =
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[UNW_ARM_R14] = 0x38,
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[UNW_ARM_R15] = 0x3c,
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#elif defined(UNW_TARGET_MIPS)
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[UNW_MIPS_R0] = 0,
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[UNW_MIPS_R1] = 1,
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[UNW_MIPS_R2] = 2,
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[UNW_MIPS_R3] = 3,
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[UNW_MIPS_R4] = 4,
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[UNW_MIPS_R5] = 5,
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[UNW_MIPS_R6] = 6,
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[UNW_MIPS_R7] = 7,
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[UNW_MIPS_R8] = 8,
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[UNW_MIPS_R9] = 9,
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[UNW_MIPS_R10] = 10,
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[UNW_MIPS_R11] = 11,
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[UNW_MIPS_R12] = 12,
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[UNW_MIPS_R13] = 13,
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[UNW_MIPS_R14] = 14,
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[UNW_MIPS_R15] = 15,
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[UNW_MIPS_R16] = 16,
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[UNW_MIPS_R17] = 17,
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[UNW_MIPS_R18] = 18,
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[UNW_MIPS_R19] = 19,
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[UNW_MIPS_R20] = 20,
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[UNW_MIPS_R21] = 21,
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[UNW_MIPS_R22] = 22,
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[UNW_MIPS_R23] = 23,
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[UNW_MIPS_R24] = 24,
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[UNW_MIPS_R25] = 25,
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[UNW_MIPS_R26] = 26,
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[UNW_MIPS_R27] = 27,
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[UNW_MIPS_R28] = 28,
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[UNW_MIPS_R29] = 29,
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[UNW_MIPS_R30] = 30,
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[UNW_MIPS_R31] = 31,
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[UNW_MIPS_PC] = 64,
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#elif defined(UNW_TARGET_SH)
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#elif defined(UNW_TARGET_AARCH64)
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[UNW_AARCH64_X0] = 0x00,
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