2006-02-01 02:29:18 +00:00
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/* tsb.S: Sparc64 TSB table handling.
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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2006-03-22 08:49:59 +00:00
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2006-02-01 02:29:18 +00:00
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#include <asm/tsb.h>
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2006-02-10 01:21:53 +00:00
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#include <asm/hypervisor.h>
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2006-03-22 08:49:59 +00:00
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#include <asm/page.h>
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#include <asm/cpudata.h>
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#include <asm/mmu.h>
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2006-02-01 02:29:18 +00:00
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.text
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.align 32
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/* Invoked from TLB miss handler, we are in the
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* MMU global registers and they are setup like
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* this:
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*
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* %g1: TSB entry pointer
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* %g2: available temporary
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* %g3: FAULT_CODE_{D,I}TLB
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* %g4: available temporary
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* %g5: available temporary
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* %g6: TAG TARGET
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2006-02-07 07:44:37 +00:00
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* %g7: available temporary, will be loaded by us with
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* the physical address base of the linux page
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2006-02-01 02:29:18 +00:00
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* tables for the current address space
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*/
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tsb_miss_dtlb:
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mov TLB_TAG_ACCESS, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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2006-02-11 08:29:34 +00:00
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ldxa [%g4] ASI_DMMU, %g4
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2006-02-01 02:29:18 +00:00
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tsb_miss_itlb:
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mov TLB_TAG_ACCESS, %g4
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ba,pt %xcc, tsb_miss_page_table_walk
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2006-02-11 08:29:34 +00:00
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ldxa [%g4] ASI_IMMU, %g4
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2006-02-01 02:29:18 +00:00
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2006-02-11 08:29:34 +00:00
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/* At this point we have:
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2006-03-22 08:49:59 +00:00
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* %g1 -- PAGE_SIZE TSB entry address
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[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g4 -- missing virtual address
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2006-02-18 02:01:02 +00:00
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* %g6 -- TAG TARGET (vaddr >> 22)
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2006-02-07 07:44:37 +00:00
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*/
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2006-02-01 02:29:18 +00:00
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tsb_miss_page_table_walk:
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2006-03-22 08:49:59 +00:00
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TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
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2006-02-27 07:24:22 +00:00
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2006-03-22 08:49:59 +00:00
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/* Before committing to a full page table walk,
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* check the huge page TSB.
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*/
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#ifdef CONFIG_HUGETLB_PAGE
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661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
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nop
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov SCRATCHPAD_UTSBREG2, %g5
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ldxa [%g5] ASI_SCRATCHPAD, %g5
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.previous
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cmp %g5, -1
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be,pt %xcc, 80f
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nop
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/* We need an aligned pair of registers containing 2 values
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* which can be easily rematerialized. %g6 and %g7 foot the
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* bill just nicely. We'll save %g6 away into %g2 for the
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* huge page TSB TAG comparison.
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*
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* Perform a huge page TSB lookup.
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*/
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mov %g6, %g2
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and %g5, 0x7, %g6
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mov 512, %g7
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andn %g5, 0x7, %g5
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sllx %g7, %g6, %g7
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srlx %g4, HPAGE_SHIFT, %g6
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sub %g7, 1, %g7
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and %g6, %g7, %g6
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sllx %g6, 4, %g6
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add %g5, %g6, %g5
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TSB_LOAD_QUAD(%g5, %g6)
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cmp %g6, %g2
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be,a,pt %xcc, tsb_tlb_reload
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mov %g7, %g5
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/* No match, remember the huge page TSB entry address,
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* and restore %g6 and %g7.
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*/
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TRAP_LOAD_TRAP_BLOCK(%g7, %g6)
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srlx %g4, 22, %g6
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80: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
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#endif
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ldx [%g7 + TRAP_PER_CPU_PGD_PADDR], %g7
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2006-02-01 02:29:18 +00:00
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[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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2006-03-22 08:49:59 +00:00
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* %g4 -- missing virtual address
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
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* %g6 -- TAG TARGET (vaddr >> 22)
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2006-03-22 08:49:59 +00:00
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* %g7 -- page table physical address
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*
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* We know that both the base PAGE_SIZE TSB and the HPAGE_SIZE
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* TSB both lack a matching entry.
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
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*/
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2006-03-22 08:49:59 +00:00
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tsb_miss_page_table_walk_sun4v_fastpath:
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USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
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2006-02-01 02:29:18 +00:00
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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2006-03-22 08:49:59 +00:00
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brgez,pn %g5, tsb_do_fault
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nop
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#ifdef CONFIG_HUGETLB_PAGE
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661: sethi %uhi(_PAGE_SZALL_4U), %g7
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sllx %g7, 32, %g7
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov _PAGE_SZALL_4V, %g7
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nop
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.previous
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and %g5, %g7, %g2
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661: sethi %uhi(_PAGE_SZHUGE_4U), %g7
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sllx %g7, 32, %g7
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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mov _PAGE_SZHUGE_4V, %g7
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nop
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.previous
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cmp %g2, %g7
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bne,pt %xcc, 60f
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nop
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/* It is a huge page, use huge page TSB entry address we
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* calculated above.
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*/
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TRAP_LOAD_TRAP_BLOCK(%g7, %g2)
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ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g2
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cmp %g2, -1
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movne %xcc, %g2, %g1
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60:
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#endif
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2006-02-01 02:29:18 +00:00
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2006-03-22 08:49:59 +00:00
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/* At this point we have:
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* %g1 -- TSB entry address
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* %g3 -- FAULT_CODE_{D,I}TLB
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* %g5 -- valid PTE
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* %g6 -- TAG TARGET (vaddr >> 22)
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*/
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tsb_reload:
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TSB_LOCK_TAG(%g1, %g2, %g7)
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2006-02-01 02:29:18 +00:00
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TSB_WRITE(%g1, %g5, %g6)
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/* Finally, load TLB and return from trap. */
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tsb_tlb_reload:
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cmp %g3, FAULT_CODE_DTLB
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bne,pn %xcc, tsb_itlb_load
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nop
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tsb_dtlb_load:
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2006-02-07 07:44:37 +00:00
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
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2006-02-01 02:29:18 +00:00
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retry
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2006-02-07 08:00:16 +00:00
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.section .sun4v_2insn_patch, "ax"
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2006-02-07 07:44:37 +00:00
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_DTLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_dtlb_load
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mov %g5, %g3
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2006-02-01 02:29:18 +00:00
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tsb_itlb_load:
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2006-03-02 06:42:18 +00:00
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/* Executable bit must be set. */
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661: andcc %g5, _PAGE_EXEC_4U, %g0
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.section .sun4v_1insn_patch, "ax"
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.word 661b
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andcc %g5, _PAGE_EXEC_4V, %g0
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.previous
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be,pn %xcc, tsb_do_fault
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nop
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2006-02-07 07:44:37 +00:00
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
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2006-02-01 02:29:18 +00:00
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retry
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2006-02-07 08:00:16 +00:00
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.section .sun4v_2insn_patch, "ax"
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2006-02-07 07:44:37 +00:00
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_ITLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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|
|
* The sun4v TLB load wants the PTE in %g3 so we fix that
|
|
|
|
* up here.
|
|
|
|
*/
|
|
|
|
ba,pt %xcc, sun4v_itlb_load
|
|
|
|
mov %g5, %g3
|
2006-02-01 02:29:18 +00:00
|
|
|
|
|
|
|
/* No valid entry in the page tables, do full fault
|
|
|
|
* processing.
|
|
|
|
*/
|
|
|
|
|
|
|
|
.globl tsb_do_fault
|
|
|
|
tsb_do_fault:
|
|
|
|
cmp %g3, FAULT_CODE_DTLB
|
2006-02-06 06:27:28 +00:00
|
|
|
|
|
|
|
661: rdpr %pstate, %g5
|
|
|
|
wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
|
2006-02-07 08:00:16 +00:00
|
|
|
.section .sun4v_2insn_patch, "ax"
|
2006-02-06 06:27:28 +00:00
|
|
|
.word 661b
|
2006-02-17 22:58:02 +00:00
|
|
|
SET_GL(1)
|
2006-02-18 02:01:02 +00:00
|
|
|
ldxa [%g0] ASI_SCRATCHPAD, %g4
|
2006-02-06 06:27:28 +00:00
|
|
|
.previous
|
|
|
|
|
2006-02-01 02:29:18 +00:00
|
|
|
bne,pn %xcc, tsb_do_itlb_fault
|
2006-02-06 06:27:28 +00:00
|
|
|
nop
|
2006-02-01 02:29:18 +00:00
|
|
|
|
|
|
|
tsb_do_dtlb_fault:
|
2006-02-07 07:44:37 +00:00
|
|
|
rdpr %tl, %g3
|
|
|
|
cmp %g3, 1
|
|
|
|
|
|
|
|
661: mov TLB_TAG_ACCESS, %g4
|
2006-02-01 02:29:18 +00:00
|
|
|
ldxa [%g4] ASI_DMMU, %g5
|
2006-02-07 08:00:16 +00:00
|
|
|
.section .sun4v_2insn_patch, "ax"
|
2006-02-07 07:44:37 +00:00
|
|
|
.word 661b
|
2006-02-18 02:01:02 +00:00
|
|
|
ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
|
2006-02-07 07:44:37 +00:00
|
|
|
nop
|
|
|
|
.previous
|
|
|
|
|
2006-02-01 02:29:18 +00:00
|
|
|
be,pt %xcc, sparc64_realfault_common
|
|
|
|
mov FAULT_CODE_DTLB, %g4
|
|
|
|
ba,pt %xcc, winfix_trampoline
|
|
|
|
nop
|
|
|
|
|
|
|
|
tsb_do_itlb_fault:
|
|
|
|
rdpr %tpc, %g5
|
|
|
|
ba,pt %xcc, sparc64_realfault_common
|
|
|
|
mov FAULT_CODE_ITLB, %g4
|
|
|
|
|
|
|
|
.globl sparc64_realfault_common
|
|
|
|
sparc64_realfault_common:
|
2006-02-01 02:34:21 +00:00
|
|
|
/* fault code in %g4, fault address in %g5, etrap will
|
|
|
|
* preserve these two values in %l4 and %l5 respectively
|
|
|
|
*/
|
2006-02-01 02:29:18 +00:00
|
|
|
ba,pt %xcc, etrap ! Save trap state
|
|
|
|
1: rd %pc, %g7 ! ...
|
2006-02-01 02:34:21 +00:00
|
|
|
stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
|
|
|
|
stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
|
2006-02-01 02:29:18 +00:00
|
|
|
call do_sparc64_fault ! Call fault handler
|
|
|
|
add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
|
|
|
|
ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
|
|
|
|
nop ! Delay slot (fill me)
|
|
|
|
|
|
|
|
winfix_trampoline:
|
|
|
|
rdpr %tpc, %g3 ! Prepare winfixup TNPC
|
|
|
|
or %g3, 0x7c, %g3 ! Compute branch offset
|
|
|
|
wrpr %g3, %tnpc ! Write it into TNPC
|
|
|
|
done ! Trap return
|
|
|
|
|
2006-02-01 02:32:04 +00:00
|
|
|
/* Insert an entry into the TSB.
|
|
|
|
*
|
2006-02-01 23:55:21 +00:00
|
|
|
* %o0: TSB entry pointer (virt or phys address)
|
2006-02-01 02:32:04 +00:00
|
|
|
* %o1: tag
|
|
|
|
* %o2: pte
|
|
|
|
*/
|
|
|
|
.align 32
|
2006-02-01 23:55:21 +00:00
|
|
|
.globl __tsb_insert
|
|
|
|
__tsb_insert:
|
2006-02-01 02:32:04 +00:00
|
|
|
rdpr %pstate, %o5
|
|
|
|
wrpr %o5, PSTATE_IE, %pstate
|
|
|
|
TSB_LOCK_TAG(%o0, %g2, %g3)
|
|
|
|
TSB_WRITE(%o0, %o2, %o1)
|
|
|
|
wrpr %o5, %pstate
|
|
|
|
retl
|
|
|
|
nop
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
|
|
|
.size __tsb_insert, .-__tsb_insert
|
2006-02-01 02:32:04 +00:00
|
|
|
|
2006-02-01 23:55:21 +00:00
|
|
|
/* Flush the given TSB entry if it has the matching
|
|
|
|
* tag.
|
|
|
|
*
|
|
|
|
* %o0: TSB entry pointer (virt or phys address)
|
|
|
|
* %o1: tag
|
|
|
|
*/
|
|
|
|
.align 32
|
|
|
|
.globl tsb_flush
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
|
|
|
.type tsb_flush,#function
|
2006-02-01 23:55:21 +00:00
|
|
|
tsb_flush:
|
|
|
|
sethi %hi(TSB_TAG_LOCK_HIGH), %g2
|
|
|
|
1: TSB_LOAD_TAG(%o0, %g1)
|
|
|
|
srlx %g1, 32, %o3
|
|
|
|
andcc %o3, %g2, %g0
|
|
|
|
bne,pn %icc, 1b
|
|
|
|
membar #LoadLoad
|
|
|
|
cmp %g1, %o1
|
2006-02-18 02:01:02 +00:00
|
|
|
mov 1, %o3
|
2006-02-01 23:55:21 +00:00
|
|
|
bne,pt %xcc, 2f
|
2006-02-18 02:01:02 +00:00
|
|
|
sllx %o3, TSB_TAG_INVALID_BIT, %o3
|
2006-02-01 23:55:21 +00:00
|
|
|
TSB_CAS_TAG(%o0, %g1, %o3)
|
|
|
|
cmp %g1, %o3
|
|
|
|
bne,pn %xcc, 1b
|
|
|
|
nop
|
|
|
|
2: retl
|
|
|
|
TSB_MEMBAR
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
|
|
|
.size tsb_flush, .-tsb_flush
|
2006-02-01 23:55:21 +00:00
|
|
|
|
2006-02-01 02:29:18 +00:00
|
|
|
/* Reload MMU related context switch state at
|
|
|
|
* schedule() time.
|
|
|
|
*
|
|
|
|
* %o0: page table physical address
|
2006-03-22 08:49:59 +00:00
|
|
|
* %o1: TSB base config pointer
|
|
|
|
* %o2: TSB huge config pointer, or NULL if none
|
|
|
|
* %o3: Hypervisor TSB descriptor physical address
|
2006-02-01 02:31:20 +00:00
|
|
|
*
|
|
|
|
* We have to run this whole thing with interrupts
|
|
|
|
* disabled so that the current cpu doesn't change
|
|
|
|
* due to preemption.
|
2006-02-01 02:29:18 +00:00
|
|
|
*/
|
2006-02-27 07:24:22 +00:00
|
|
|
.align 32
|
2006-02-01 02:31:20 +00:00
|
|
|
.globl __tsb_context_switch
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
|
|
|
.type __tsb_context_switch,#function
|
2006-02-01 02:31:20 +00:00
|
|
|
__tsb_context_switch:
|
2006-03-22 08:49:59 +00:00
|
|
|
rdpr %pstate, %g1
|
|
|
|
wrpr %g1, PSTATE_IE, %pstate
|
|
|
|
|
|
|
|
TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
|
2006-02-01 02:29:18 +00:00
|
|
|
|
2006-02-01 02:31:20 +00:00
|
|
|
stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
|
2006-02-01 02:29:18 +00:00
|
|
|
|
2006-03-22 08:49:59 +00:00
|
|
|
ldx [%o1 + TSB_CONFIG_REG_VAL], %o0
|
|
|
|
brz,pt %o2, 1f
|
|
|
|
mov -1, %g3
|
|
|
|
|
|
|
|
ldx [%o2 + TSB_CONFIG_REG_VAL], %g3
|
|
|
|
|
|
|
|
1: stx %g3, [%g2 + TRAP_PER_CPU_TSB_HUGE]
|
|
|
|
|
|
|
|
sethi %hi(tlb_type), %g2
|
|
|
|
lduw [%g2 + %lo(tlb_type)], %g2
|
|
|
|
cmp %g2, 3
|
|
|
|
bne,pt %icc, 50f
|
2006-02-10 01:21:53 +00:00
|
|
|
nop
|
|
|
|
|
|
|
|
/* Hypervisor TSB switch. */
|
2006-03-22 08:49:59 +00:00
|
|
|
mov SCRATCHPAD_UTSBREG1, %o5
|
|
|
|
stxa %o0, [%o5] ASI_SCRATCHPAD
|
|
|
|
mov SCRATCHPAD_UTSBREG2, %o5
|
|
|
|
stxa %g3, [%o5] ASI_SCRATCHPAD
|
|
|
|
|
|
|
|
mov 2, %o0
|
|
|
|
cmp %g3, -1
|
|
|
|
move %xcc, 1, %o0
|
2006-02-16 05:16:42 +00:00
|
|
|
|
2006-02-10 06:57:21 +00:00
|
|
|
mov HV_FAST_MMU_TSB_CTXNON0, %o5
|
2006-03-22 08:49:59 +00:00
|
|
|
mov %o3, %o1
|
2006-02-10 01:21:53 +00:00
|
|
|
ta HV_FAST_TRAP
|
|
|
|
|
2006-03-22 08:49:59 +00:00
|
|
|
/* Finish up. */
|
2006-02-10 01:21:53 +00:00
|
|
|
ba,pt %xcc, 9f
|
2006-03-22 08:49:59 +00:00
|
|
|
nop
|
2006-02-01 02:29:18 +00:00
|
|
|
|
2006-02-10 01:21:53 +00:00
|
|
|
/* SUN4U TSB switch. */
|
2006-03-22 08:49:59 +00:00
|
|
|
50: mov TSB_REG, %o5
|
|
|
|
stxa %o0, [%o5] ASI_DMMU
|
2006-02-10 01:21:53 +00:00
|
|
|
membar #Sync
|
2006-03-22 08:49:59 +00:00
|
|
|
stxa %o0, [%o5] ASI_IMMU
|
2006-02-01 02:29:18 +00:00
|
|
|
membar #Sync
|
|
|
|
|
2006-03-22 08:49:59 +00:00
|
|
|
2: ldx [%o1 + TSB_CONFIG_MAP_VADDR], %o4
|
|
|
|
brz %o4, 9f
|
|
|
|
ldx [%o1 + TSB_CONFIG_MAP_PTE], %o5
|
2006-02-01 02:29:18 +00:00
|
|
|
|
2006-02-10 01:21:53 +00:00
|
|
|
sethi %hi(sparc64_highest_unlocked_tlb_ent), %g2
|
2006-03-22 08:49:59 +00:00
|
|
|
mov TLB_TAG_ACCESS, %g3
|
2006-02-10 01:21:53 +00:00
|
|
|
lduw [%g2 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
|
2006-03-22 08:49:59 +00:00
|
|
|
stxa %o4, [%g3] ASI_DMMU
|
2006-02-01 02:33:12 +00:00
|
|
|
membar #Sync
|
|
|
|
sllx %g2, 3, %g2
|
2006-03-22 08:49:59 +00:00
|
|
|
stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
brz,pt %o2, 9f
|
|
|
|
nop
|
|
|
|
|
|
|
|
ldx [%o2 + TSB_CONFIG_MAP_VADDR], %o4
|
|
|
|
ldx [%o2 + TSB_CONFIG_MAP_PTE], %o5
|
|
|
|
mov TLB_TAG_ACCESS, %g3
|
|
|
|
stxa %o4, [%g3] ASI_DMMU
|
|
|
|
membar #Sync
|
|
|
|
sub %g2, (1 << 3), %g2
|
|
|
|
stxa %o5, [%g2] ASI_DTLB_DATA_ACCESS
|
2006-02-01 02:33:12 +00:00
|
|
|
membar #Sync
|
2006-03-22 08:49:59 +00:00
|
|
|
|
2006-02-01 02:29:18 +00:00
|
|
|
9:
|
2006-03-22 08:49:59 +00:00
|
|
|
wrpr %g1, %pstate
|
2006-02-01 02:29:18 +00:00
|
|
|
|
|
|
|
retl
|
2006-02-01 02:31:20 +00:00
|
|
|
nop
|
[SPARC64]: Fix and re-enable dynamic TSB sizing.
This is good for up to %50 performance improvement of some test cases.
The problem has been the race conditions, and hopefully I've plugged
them all up here.
1) There was a serious race in switch_mm() wrt. lazy TLB
switching to and from kernel threads.
We could erroneously skip a tsb_context_switch() and thus
use a stale TSB across a TSB grow event.
There is a big comment now in that function describing
exactly how it can happen.
2) All code paths that do something with the TSB need to be
guarded with the mm->context.lock spinlock. This makes
page table flushing paths properly synchronize with both
TSB growing and TLB context changes.
3) TSB growing events are moved to the end of successful fault
processing. Previously it was in update_mmu_cache() but
that is deadlock prone. At the end of do_sparc64_fault()
we hold no spinlocks that could deadlock the TSB grow
sequence. We also have dropped the address space semaphore.
While we're here, add prefetching to the copy_tsb() routine
and put it in assembler into the tsb.S file. This piece of
code is quite time critical.
There are some small negative side effects to this code which
can be improved upon. In particular we grab the mm->context.lock
even for the tsb insert done by update_mmu_cache() now and that's
a bit excessive. We can get rid of that locking, and the same
lock taking in flush_tsb_user(), by disabling PSTATE_IE around
the whole operation including the capturing of the tsb pointer
and tsb_nentries value. That would work because anyone growing
the TSB won't free up the old TSB until all cpus respond to the
TSB change cross call.
I'm not quite so confident in that optimization to put it in
right now, but eventually we might be able to and the description
is here for reference.
This code seems very solid now. It passes several parallel GCC
bootstrap builds, and our favorite "nut cruncher" stress test which is
a full "make -j8192" build of a "make allmodconfig" kernel. That puts
about 256 processes on each cpu's run queue, makes lots of process cpu
migrations occur, causes lots of page table and TLB flushing activity,
incurs many context version number changes, and it swaps the machine
real far out to disk even though there is 16GB of ram on this test
system. :-)
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-16 10:02:32 +00:00
|
|
|
.size __tsb_context_switch, .-__tsb_context_switch
|
|
|
|
|
|
|
|
#define TSB_PASS_BITS ((1 << TSB_TAG_LOCK_BIT) | \
|
|
|
|
(1 << TSB_TAG_INVALID_BIT))
|
|
|
|
|
|
|
|
.align 32
|
|
|
|
.globl copy_tsb
|
|
|
|
.type copy_tsb,#function
|
|
|
|
copy_tsb: /* %o0=old_tsb_base, %o1=old_tsb_size
|
|
|
|
* %o2=new_tsb_base, %o3=new_tsb_size
|
|
|
|
*/
|
|
|
|
sethi %uhi(TSB_PASS_BITS), %g7
|
|
|
|
srlx %o3, 4, %o3
|
|
|
|
add %o0, %o1, %g1 /* end of old tsb */
|
|
|
|
sllx %g7, 32, %g7
|
|
|
|
sub %o3, 1, %o3 /* %o3 == new tsb hash mask */
|
|
|
|
|
|
|
|
661: prefetcha [%o0] ASI_N, #one_read
|
|
|
|
.section .tsb_phys_patch, "ax"
|
|
|
|
.word 661b
|
|
|
|
prefetcha [%o0] ASI_PHYS_USE_EC, #one_read
|
|
|
|
.previous
|
|
|
|
|
|
|
|
90: andcc %o0, (64 - 1), %g0
|
|
|
|
bne 1f
|
|
|
|
add %o0, 64, %o5
|
|
|
|
|
|
|
|
661: prefetcha [%o5] ASI_N, #one_read
|
|
|
|
.section .tsb_phys_patch, "ax"
|
|
|
|
.word 661b
|
|
|
|
prefetcha [%o5] ASI_PHYS_USE_EC, #one_read
|
|
|
|
.previous
|
|
|
|
|
|
|
|
1: TSB_LOAD_QUAD(%o0, %g2) /* %g2/%g3 == TSB entry */
|
|
|
|
andcc %g2, %g7, %g0 /* LOCK or INVALID set? */
|
|
|
|
bne,pn %xcc, 80f /* Skip it */
|
|
|
|
sllx %g2, 22, %o4 /* TAG --> VADDR */
|
|
|
|
|
|
|
|
/* This can definitely be computed faster... */
|
|
|
|
srlx %o0, 4, %o5 /* Build index */
|
|
|
|
and %o5, 511, %o5 /* Mask index */
|
|
|
|
sllx %o5, PAGE_SHIFT, %o5 /* Put into vaddr position */
|
|
|
|
or %o4, %o5, %o4 /* Full VADDR. */
|
|
|
|
srlx %o4, PAGE_SHIFT, %o4 /* Shift down to create index */
|
|
|
|
and %o4, %o3, %o4 /* Mask with new_tsb_nents-1 */
|
|
|
|
sllx %o4, 4, %o4 /* Shift back up into tsb ent offset */
|
|
|
|
TSB_STORE(%o2 + %o4, %g2) /* Store TAG */
|
|
|
|
add %o4, 0x8, %o4 /* Advance to TTE */
|
|
|
|
TSB_STORE(%o2 + %o4, %g3) /* Store TTE */
|
|
|
|
|
|
|
|
80: add %o0, 16, %o0
|
|
|
|
cmp %o0, %g1
|
|
|
|
bne,pt %xcc, 90b
|
|
|
|
nop
|
|
|
|
|
|
|
|
retl
|
|
|
|
TSB_MEMBAR
|
|
|
|
.size copy_tsb, .-copy_tsb
|
2006-03-19 07:55:11 +00:00
|
|
|
|
|
|
|
/* Set the invalid bit in all TSB entries. */
|
|
|
|
.align 32
|
|
|
|
.globl tsb_init
|
|
|
|
.type tsb_init,#function
|
|
|
|
tsb_init: /* %o0 = TSB vaddr, %o1 = size in bytes */
|
|
|
|
prefetch [%o0 + 0x000], #n_writes
|
|
|
|
mov 1, %g1
|
|
|
|
prefetch [%o0 + 0x040], #n_writes
|
|
|
|
sllx %g1, TSB_TAG_INVALID_BIT, %g1
|
|
|
|
prefetch [%o0 + 0x080], #n_writes
|
|
|
|
1: prefetch [%o0 + 0x0c0], #n_writes
|
|
|
|
stx %g1, [%o0 + 0x00]
|
|
|
|
stx %g1, [%o0 + 0x10]
|
|
|
|
stx %g1, [%o0 + 0x20]
|
|
|
|
stx %g1, [%o0 + 0x30]
|
|
|
|
prefetch [%o0 + 0x100], #n_writes
|
|
|
|
stx %g1, [%o0 + 0x40]
|
|
|
|
stx %g1, [%o0 + 0x50]
|
|
|
|
stx %g1, [%o0 + 0x60]
|
|
|
|
stx %g1, [%o0 + 0x70]
|
|
|
|
prefetch [%o0 + 0x140], #n_writes
|
|
|
|
stx %g1, [%o0 + 0x80]
|
|
|
|
stx %g1, [%o0 + 0x90]
|
|
|
|
stx %g1, [%o0 + 0xa0]
|
|
|
|
stx %g1, [%o0 + 0xb0]
|
|
|
|
prefetch [%o0 + 0x180], #n_writes
|
|
|
|
stx %g1, [%o0 + 0xc0]
|
|
|
|
stx %g1, [%o0 + 0xd0]
|
|
|
|
stx %g1, [%o0 + 0xe0]
|
|
|
|
stx %g1, [%o0 + 0xf0]
|
|
|
|
subcc %o1, 0x100, %o1
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
add %o0, 0x100, %o0
|
|
|
|
retl
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
nop
|
|
|
|
.size tsb_init, .-tsb_init
|
|
|
|
|
|
|
|
.globl NGtsb_init
|
|
|
|
.type NGtsb_init,#function
|
|
|
|
NGtsb_init:
|
|
|
|
rd %asi, %g2
|
|
|
|
mov 1, %g1
|
|
|
|
wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
|
|
|
|
sllx %g1, TSB_TAG_INVALID_BIT, %g1
|
|
|
|
1: stxa %g1, [%o0 + 0x00] %asi
|
|
|
|
stxa %g1, [%o0 + 0x10] %asi
|
|
|
|
stxa %g1, [%o0 + 0x20] %asi
|
|
|
|
stxa %g1, [%o0 + 0x30] %asi
|
|
|
|
stxa %g1, [%o0 + 0x40] %asi
|
|
|
|
stxa %g1, [%o0 + 0x50] %asi
|
|
|
|
stxa %g1, [%o0 + 0x60] %asi
|
|
|
|
stxa %g1, [%o0 + 0x70] %asi
|
|
|
|
stxa %g1, [%o0 + 0x80] %asi
|
|
|
|
stxa %g1, [%o0 + 0x90] %asi
|
|
|
|
stxa %g1, [%o0 + 0xa0] %asi
|
|
|
|
stxa %g1, [%o0 + 0xb0] %asi
|
|
|
|
stxa %g1, [%o0 + 0xc0] %asi
|
|
|
|
stxa %g1, [%o0 + 0xd0] %asi
|
|
|
|
stxa %g1, [%o0 + 0xe0] %asi
|
|
|
|
stxa %g1, [%o0 + 0xf0] %asi
|
|
|
|
subcc %o1, 0x100, %o1
|
|
|
|
bne,pt %xcc, 1b
|
|
|
|
add %o0, 0x100, %o0
|
2007-03-19 20:27:33 +00:00
|
|
|
membar #Sync
|
2006-03-19 07:55:11 +00:00
|
|
|
retl
|
|
|
|
wr %g2, 0x0, %asi
|
|
|
|
.size NGtsb_init, .-NGtsb_init
|