2008-04-24 20:58:29 +00:00
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/*
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* File: arch/blackfin/mach-common/cpufreq.c
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* Based on:
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* Author:
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*
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* Created:
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* Description: Blackfin core clock scaling
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*
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* Modified:
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/fs.h>
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#include <asm/blackfin.h>
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#include <asm/time.h>
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/* this is the table of CCLK frequencies, in Hz */
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/* .index is the entry in the auxillary dpm_state_table[] */
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static struct cpufreq_frequency_table bfin_freq_table[] = {
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 0,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 1,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 2,
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},
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{
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.frequency = CPUFREQ_TABLE_END,
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.index = 0,
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},
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};
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static struct bfin_dpm_state {
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unsigned int csel; /* system clock divider */
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unsigned int tscale; /* change the divider on the core timer interrupt */
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} dpm_state_table[3];
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2008-05-07 03:41:26 +00:00
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/*
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normalized to maximum frequncy offset for CYCLES,
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used in time-ts cycles clock source, but could be used
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somewhere also.
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*/
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unsigned long long __bfin_cycles_off;
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unsigned int __bfin_cycles_mod;
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2008-04-24 20:58:29 +00:00
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/**************************************************************************/
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2008-10-28 06:18:29 +00:00
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static unsigned int bfin_getfreq_khz(unsigned int cpu)
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2008-04-24 20:58:29 +00:00
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{
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/* The driver only support single cpu */
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if (cpu != 0)
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return -1;
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2008-10-28 06:18:29 +00:00
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return get_cclk() / 1000;
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2008-04-24 20:58:29 +00:00
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}
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static int bfin_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int index, plldiv, tscale;
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unsigned long flags, cclk_hz;
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struct cpufreq_freqs freqs;
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2008-05-07 03:41:26 +00:00
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cycles_t cycles;
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2008-04-24 20:58:29 +00:00
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if (cpufreq_frequency_table_target(policy, bfin_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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cclk_hz = bfin_freq_table[index].frequency;
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2008-10-28 06:18:29 +00:00
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freqs.old = bfin_getfreq_khz(0);
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2008-04-24 20:58:29 +00:00
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freqs.new = cclk_hz;
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freqs.cpu = 0;
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pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
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cclk_hz, target_freq, freqs.old);
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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2009-01-07 15:14:39 +00:00
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local_irq_save_hw(flags);
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2008-04-24 20:58:29 +00:00
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plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
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tscale = dpm_state_table[index].tscale;
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bfin_write_PLL_DIV(plldiv);
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/* we have to adjust the core timer, because it is using cclk */
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bfin_write_TSCALE(tscale);
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2008-05-07 03:41:26 +00:00
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cycles = get_cycles();
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2008-04-24 20:58:29 +00:00
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SSYNC();
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2009-01-07 15:14:39 +00:00
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cycles += 10; /* ~10 cycles we lose after get_cycles() */
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2008-05-07 03:41:26 +00:00
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__bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
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__bfin_cycles_mod = index;
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2009-01-07 15:14:39 +00:00
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local_irq_restore_hw(flags);
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2008-05-07 03:41:26 +00:00
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/* TODO: just test case for cycles clock source, remove later */
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pr_debug("cpufreq: done\n");
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2008-04-24 20:58:29 +00:00
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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static int bfin_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, bfin_freq_table);
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}
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static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned long cclk, sclk, csel, min_cclk;
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int index;
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if (policy->cpu != 0)
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return -EINVAL;
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2008-10-28 06:18:29 +00:00
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cclk = get_cclk() / 1000;
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sclk = get_sclk() / 1000;
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2008-04-24 20:58:29 +00:00
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2009-05-07 10:04:19 +00:00
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#if ANOMALY_05000273 || ANOMALY_05000274 || \
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2009-06-16 09:48:33 +00:00
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(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
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2008-04-24 20:58:29 +00:00
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min_cclk = sclk * 2;
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#else
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min_cclk = sclk;
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#endif
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csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
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for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
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bfin_freq_table[index].frequency = cclk >> index;
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dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
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dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
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2008-10-28 06:18:29 +00:00
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pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
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2008-04-24 20:58:29 +00:00
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bfin_freq_table[index].frequency,
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dpm_state_table[index].csel,
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dpm_state_table[index].tscale);
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}
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policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
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/*Now ,only support one cpu */
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policy->cur = cclk;
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cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
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return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
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}
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static struct freq_attr *bfin_freq_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver bfin_driver = {
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.verify = bfin_verify_speed,
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.target = bfin_target,
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2008-10-28 06:18:29 +00:00
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.get = bfin_getfreq_khz,
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2008-04-24 20:58:29 +00:00
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.init = __bfin_cpu_init,
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.name = "bfin cpufreq",
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.owner = THIS_MODULE,
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.attr = bfin_freq_attr,
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};
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static int __init bfin_cpu_init(void)
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{
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return cpufreq_register_driver(&bfin_driver);
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}
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static void __exit bfin_cpu_exit(void)
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{
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cpufreq_unregister_driver(&bfin_driver);
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}
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MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
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MODULE_DESCRIPTION("cpufreq driver for Blackfin");
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MODULE_LICENSE("GPL");
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module_init(bfin_cpu_init);
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module_exit(bfin_cpu_exit);
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