usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
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/**
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* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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* All rights reserved.
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
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const struct dwc3_event_depevt *event);
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static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
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{
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switch (state) {
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case EP0_UNCONNECTED:
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return "Unconnected";
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case EP0_IDLE:
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return "Idle";
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case EP0_IN_DATA_PHASE:
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return "IN Data Phase";
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case EP0_OUT_DATA_PHASE:
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return "OUT Data Phase";
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case EP0_IN_WAIT_GADGET:
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return "IN Wait Gadget";
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case EP0_OUT_WAIT_GADGET:
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return "OUT Wait Gadget";
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case EP0_IN_WAIT_NRDY:
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return "IN Wait NRDY";
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case EP0_OUT_WAIT_NRDY:
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return "OUT Wait NRDY";
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case EP0_IN_STATUS_PHASE:
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return "IN Status Phase";
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case EP0_OUT_STATUS_PHASE:
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return "OUT Status Phase";
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case EP0_STALL:
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return "Stall";
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default:
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return "UNKNOWN";
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}
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}
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static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
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u32 len)
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{
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struct dwc3_gadget_ep_cmd_params params;
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struct dwc3_trb_hw *trb_hw;
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struct dwc3_trb trb;
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struct dwc3_ep *dep;
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int ret;
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dep = dwc->eps[epnum];
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trb_hw = dwc->ep0_trb;
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memset(&trb, 0, sizeof(trb));
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switch (dwc->ep0state) {
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case EP0_IDLE:
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trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
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break;
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case EP0_IN_WAIT_NRDY:
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case EP0_OUT_WAIT_NRDY:
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case EP0_IN_STATUS_PHASE:
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case EP0_OUT_STATUS_PHASE:
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if (dwc->three_stage_setup)
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trb.trbctl = DWC3_TRBCTL_CONTROL_STATUS3;
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else
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trb.trbctl = DWC3_TRBCTL_CONTROL_STATUS2;
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if (dwc->ep0state == EP0_IN_WAIT_NRDY)
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dwc->ep0state = EP0_IN_STATUS_PHASE;
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else if (dwc->ep0state == EP0_OUT_WAIT_NRDY)
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dwc->ep0state = EP0_OUT_STATUS_PHASE;
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break;
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case EP0_IN_WAIT_GADGET:
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dwc->ep0state = EP0_IN_WAIT_NRDY;
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return 0;
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break;
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case EP0_OUT_WAIT_GADGET:
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dwc->ep0state = EP0_OUT_WAIT_NRDY;
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return 0;
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break;
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case EP0_IN_DATA_PHASE:
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case EP0_OUT_DATA_PHASE:
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trb.trbctl = DWC3_TRBCTL_CONTROL_DATA;
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break;
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default:
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dev_err(dwc->dev, "%s() can't in state %d\n", __func__,
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dwc->ep0state);
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return -EINVAL;
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}
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trb.bplh = buf_dma;
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trb.length = len;
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trb.hwo = 1;
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trb.lst = 1;
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trb.ioc = 1;
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trb.isp_imi = 1;
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dwc3_trb_to_hw(&trb, trb_hw);
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memset(¶ms, 0, sizeof(params));
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params.param0.depstrtxfer.transfer_desc_addr_high =
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upper_32_bits(dwc->ep0_trb_addr);
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params.param1.depstrtxfer.transfer_desc_addr_low =
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lower_32_bits(dwc->ep0_trb_addr);
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ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
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DWC3_DEPCMD_STARTTRANSFER, ¶ms);
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if (ret < 0) {
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dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
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return ret;
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}
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dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
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dep->number);
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return 0;
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}
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static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
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struct dwc3_request *req)
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{
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struct dwc3 *dwc = dep->dwc;
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int ret;
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req->request.actual = 0;
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req->request.status = -EINPROGRESS;
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req->direction = dep->direction;
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req->epnum = dep->number;
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list_add_tail(&req->list, &dep->request_list);
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dwc3_map_buffer_to_dma(req);
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ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
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req->request.length);
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if (ret < 0) {
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list_del(&req->list);
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dwc3_unmap_buffer_from_dma(req);
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}
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return ret;
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}
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
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gfp_t gfp_flags)
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{
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struct dwc3_request *req = to_dwc3_request(request);
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struct dwc3_ep *dep = to_dwc3_ep(ep);
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struct dwc3 *dwc = dep->dwc;
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unsigned long flags;
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int ret;
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switch (dwc->ep0state) {
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case EP0_IN_DATA_PHASE:
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case EP0_IN_WAIT_GADGET:
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case EP0_IN_WAIT_NRDY:
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case EP0_IN_STATUS_PHASE:
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dep = dwc->eps[1];
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break;
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case EP0_OUT_DATA_PHASE:
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case EP0_OUT_WAIT_GADGET:
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case EP0_OUT_WAIT_NRDY:
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case EP0_OUT_STATUS_PHASE:
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dep = dwc->eps[0];
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&dwc->lock, flags);
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if (!dep->desc) {
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dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
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request, dep->name);
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ret = -ESHUTDOWN;
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goto out;
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}
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/* we share one TRB for ep0/1 */
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if (!list_empty(&dwc->eps[0]->request_list) ||
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!list_empty(&dwc->eps[1]->request_list) ||
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dwc->ep0_status_pending) {
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ret = -EBUSY;
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goto out;
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}
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dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
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request, dep->name, request->length,
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dwc3_ep0_state_string(dwc->ep0state));
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ret = __dwc3_gadget_ep0_queue(dep, req);
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out:
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spin_unlock_irqrestore(&dwc->lock, flags);
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return ret;
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}
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static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
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{
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/* stall is always issued on EP0 */
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__dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
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dwc->eps[0]->flags &= ~DWC3_EP_STALL;
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dwc->ep0state = EP0_IDLE;
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dwc3_ep0_out_start(dwc);
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}
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void dwc3_ep0_out_start(struct dwc3 *dwc)
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{
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struct dwc3_ep *dep;
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int ret;
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dep = dwc->eps[0];
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ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8);
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WARN_ON(ret < 0);
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}
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/*
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* Send a zero length packet for the status phase of the control transfer
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*/
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static void dwc3_ep0_do_setup_status(struct dwc3 *dwc,
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const struct dwc3_event_depevt *event)
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{
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struct dwc3_ep *dep;
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int ret;
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u32 epnum;
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epnum = event->endpoint_number;
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dep = dwc->eps[epnum];
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if (epnum)
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dwc->ep0state = EP0_IN_STATUS_PHASE;
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else
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dwc->ep0state = EP0_OUT_STATUS_PHASE;
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/*
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* Not sure Why I need a buffer for a zero transfer. Maybe the
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* HW reacts strange on a NULL pointer
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*/
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ret = dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr, 0);
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if (ret) {
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dev_dbg(dwc->dev, "failed to start transfer, stalling\n");
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dwc3_ep0_stall_and_restart(dwc);
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}
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}
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static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
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{
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struct dwc3_ep *dep;
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u32 windex = le16_to_cpu(wIndex_le);
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u32 epnum;
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epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
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if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
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epnum |= 1;
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dep = dwc->eps[epnum];
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if (dep->flags & DWC3_EP_ENABLED)
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return dep;
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return NULL;
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}
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static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
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{
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u32 epnum;
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if (dwc->ep0state == EP0_IN_DATA_PHASE)
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epnum = 1;
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else
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epnum = 0;
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dwc3_ep0_start_trans(dwc, epnum, dwc->ctrl_req_addr,
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dwc->ep0_usb_req.length);
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dwc->ep0_status_pending = 1;
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}
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/*
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* ch 9.4.5
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*/
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static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
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{
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struct dwc3_ep *dep;
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u32 recip;
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u16 usb_status = 0;
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__le16 *response_pkt;
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recip = ctrl->bRequestType & USB_RECIP_MASK;
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switch (recip) {
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case USB_RECIP_DEVICE:
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/*
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|
|
* We are self-powered. U1/U2/LTM will be set later
|
|
|
|
* once we handle this states. RemoteWakeup is 0 on SS
|
|
|
|
*/
|
|
|
|
usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_RECIP_INTERFACE:
|
|
|
|
/*
|
|
|
|
* Function Remote Wake Capable D0
|
|
|
|
* Function Remote Wakeup D1
|
|
|
|
*/
|
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_RECIP_ENDPOINT:
|
|
|
|
dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
|
|
|
|
if (!dep)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (dep->flags & DWC3_EP_STALL)
|
|
|
|
usb_status = 1 << USB_ENDPOINT_HALT;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
};
|
|
|
|
|
|
|
|
response_pkt = (__le16 *) dwc->setup_buf;
|
|
|
|
*response_pkt = cpu_to_le16(usb_status);
|
|
|
|
dwc->ep0_usb_req.length = sizeof(*response_pkt);
|
|
|
|
dwc3_ep0_send_status_response(dwc);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
|
|
|
|
struct usb_ctrlrequest *ctrl, int set)
|
|
|
|
{
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
u32 recip;
|
|
|
|
u32 wValue;
|
|
|
|
u32 wIndex;
|
|
|
|
u32 reg;
|
|
|
|
int ret;
|
|
|
|
u32 mode;
|
|
|
|
|
|
|
|
wValue = le16_to_cpu(ctrl->wValue);
|
|
|
|
wIndex = le16_to_cpu(ctrl->wIndex);
|
|
|
|
recip = ctrl->bRequestType & USB_RECIP_MASK;
|
|
|
|
switch (recip) {
|
|
|
|
case USB_RECIP_DEVICE:
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 9.4.1 says only only for SS, in AddressState only for
|
|
|
|
* default control pipe
|
|
|
|
*/
|
|
|
|
switch (wValue) {
|
|
|
|
case USB_DEVICE_U1_ENABLE:
|
|
|
|
case USB_DEVICE_U2_ENABLE:
|
|
|
|
case USB_DEVICE_LTM_ENABLE:
|
|
|
|
if (dwc->dev_state != DWC3_CONFIGURED_STATE)
|
|
|
|
return -EINVAL;
|
|
|
|
if (dwc->speed != DWC3_DSTS_SUPERSPEED)
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX add U[12] & LTM */
|
|
|
|
switch (wValue) {
|
|
|
|
case USB_DEVICE_REMOTE_WAKEUP:
|
|
|
|
break;
|
|
|
|
case USB_DEVICE_U1_ENABLE:
|
|
|
|
break;
|
|
|
|
case USB_DEVICE_U2_ENABLE:
|
|
|
|
break;
|
|
|
|
case USB_DEVICE_LTM_ENABLE:
|
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_DEVICE_TEST_MODE:
|
|
|
|
if ((wIndex & 0xff) != 0)
|
|
|
|
return -EINVAL;
|
|
|
|
if (!set)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mode = wIndex >> 8;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
|
|
|
|
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case TEST_J:
|
|
|
|
case TEST_K:
|
|
|
|
case TEST_SE0_NAK:
|
|
|
|
case TEST_PACKET:
|
|
|
|
case TEST_FORCE_EN:
|
|
|
|
reg |= mode << 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_RECIP_INTERFACE:
|
|
|
|
switch (wValue) {
|
|
|
|
case USB_INTRF_FUNC_SUSPEND:
|
|
|
|
if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
|
|
|
|
/* XXX enable Low power suspend */
|
|
|
|
;
|
|
|
|
if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
|
|
|
|
/* XXX enable remote wakeup */
|
|
|
|
;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case USB_RECIP_ENDPOINT:
|
|
|
|
switch (wValue) {
|
|
|
|
case USB_ENDPOINT_HALT:
|
|
|
|
|
|
|
|
dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
|
|
|
|
if (!dep)
|
|
|
|
return -EINVAL;
|
|
|
|
ret = __dwc3_gadget_ep_set_halt(dep, set);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
};
|
|
|
|
|
|
|
|
dwc->ep0state = EP0_IN_WAIT_NRDY;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
u32 addr;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
addr = le16_to_cpu(ctrl->wValue);
|
|
|
|
if (addr > 127)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (dwc->dev_state) {
|
|
|
|
case DWC3_DEFAULT_STATE:
|
|
|
|
case DWC3_ADDRESS_STATE:
|
|
|
|
/*
|
|
|
|
* Not sure if we should program DevAddr now or later
|
|
|
|
*/
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
|
|
|
|
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
|
|
|
|
reg |= DWC3_DCFG_DEVADDR(addr);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
|
|
|
|
|
|
|
|
if (addr)
|
|
|
|
dwc->dev_state = DWC3_ADDRESS_STATE;
|
|
|
|
else
|
|
|
|
dwc->dev_state = DWC3_DEFAULT_STATE;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DWC3_CONFIGURED_STATE:
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
dwc->ep0state = EP0_IN_WAIT_NRDY;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
spin_unlock(&dwc->lock);
|
|
|
|
ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
|
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
|
|
{
|
|
|
|
u32 cfg;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
cfg = le16_to_cpu(ctrl->wValue);
|
|
|
|
|
|
|
|
switch (dwc->dev_state) {
|
|
|
|
case DWC3_DEFAULT_STATE:
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DWC3_ADDRESS_STATE:
|
|
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
|
|
/* if the cfg matches and the cfg is non zero */
|
|
|
|
if (!ret && cfg)
|
|
|
|
dwc->dev_state = DWC3_CONFIGURED_STATE;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DWC3_CONFIGURED_STATE:
|
|
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
|
|
if (!cfg)
|
|
|
|
dwc->dev_state = DWC3_ADDRESS_STATE;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (ctrl->bRequest) {
|
|
|
|
case USB_REQ_GET_STATUS:
|
|
|
|
dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
|
|
|
|
ret = dwc3_ep0_handle_status(dwc, ctrl);
|
|
|
|
break;
|
|
|
|
case USB_REQ_CLEAR_FEATURE:
|
|
|
|
dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
|
|
|
|
ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_FEATURE:
|
|
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
|
|
|
|
ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_ADDRESS:
|
|
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
|
|
|
|
ret = dwc3_ep0_set_address(dwc, ctrl);
|
|
|
|
break;
|
|
|
|
case USB_REQ_SET_CONFIGURATION:
|
|
|
|
dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
|
|
|
|
ret = dwc3_ep0_set_config(dwc, ctrl);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
|
|
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
|
|
break;
|
|
|
|
};
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
|
|
|
|
int ret;
|
|
|
|
u32 len;
|
|
|
|
|
|
|
|
if (!dwc->gadget_driver)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
len = le16_to_cpu(ctrl->wLength);
|
|
|
|
if (!len) {
|
|
|
|
dwc->ep0state = EP0_IN_WAIT_GADGET;
|
|
|
|
dwc->three_stage_setup = 0;
|
|
|
|
} else {
|
|
|
|
dwc->three_stage_setup = 1;
|
|
|
|
if (ctrl->bRequestType & USB_DIR_IN)
|
|
|
|
dwc->ep0state = EP0_IN_DATA_PHASE;
|
|
|
|
else
|
|
|
|
dwc->ep0state = EP0_OUT_DATA_PHASE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
|
|
|
|
ret = dwc3_ep0_std_request(dwc, ctrl);
|
|
|
|
else
|
|
|
|
ret = dwc3_ep0_delegate_req(dwc, ctrl);
|
|
|
|
|
|
|
|
if (ret >= 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
|
|
|
dwc3_ep0_stall_and_restart(dwc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_ep0_complete_data(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
struct dwc3_request *r = NULL;
|
|
|
|
struct usb_request *ur;
|
|
|
|
struct dwc3_trb trb;
|
|
|
|
struct dwc3_ep *dep;
|
2011-08-26 23:30:33 +00:00
|
|
|
u32 transferred;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
u8 epnum;
|
|
|
|
|
|
|
|
epnum = event->endpoint_number;
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
|
|
|
|
if (!dwc->ep0_status_pending) {
|
|
|
|
r = next_request(&dep->request_list);
|
|
|
|
ur = &r->request;
|
|
|
|
} else {
|
|
|
|
ur = &dwc->ep0_usb_req;
|
|
|
|
dwc->ep0_status_pending = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc3_trb_to_nat(dwc->ep0_trb, &trb);
|
|
|
|
|
2011-08-26 23:30:33 +00:00
|
|
|
transferred = ur->length - trb.length;
|
|
|
|
ur->actual += transferred;
|
usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 15:10:58 +00:00
|
|
|
|
|
|
|
if ((epnum & 1) && ur->actual < ur->length) {
|
|
|
|
/* for some reason we did not get everything out */
|
|
|
|
|
|
|
|
dwc3_ep0_stall_and_restart(dwc);
|
|
|
|
dwc3_gadget_giveback(dep, r, -ECONNRESET);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* handle the case where we have to send a zero packet. This
|
|
|
|
* seems to be case when req.length > maxpacket. Could it be?
|
|
|
|
*/
|
|
|
|
/* The transfer is complete, wait for HOST */
|
|
|
|
if (epnum & 1)
|
|
|
|
dwc->ep0state = EP0_IN_WAIT_NRDY;
|
|
|
|
else
|
|
|
|
dwc->ep0state = EP0_OUT_WAIT_NRDY;
|
|
|
|
|
|
|
|
if (r)
|
|
|
|
dwc3_gadget_giveback(dep, r, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_ep0_complete_req(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
struct dwc3_request *r;
|
|
|
|
struct dwc3_ep *dep;
|
|
|
|
u8 epnum;
|
|
|
|
|
|
|
|
epnum = event->endpoint_number;
|
|
|
|
dep = dwc->eps[epnum];
|
|
|
|
|
|
|
|
if (!list_empty(&dep->request_list)) {
|
|
|
|
r = next_request(&dep->request_list);
|
|
|
|
|
|
|
|
dwc3_gadget_giveback(dep, r, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
dwc->ep0state = EP0_IDLE;
|
|
|
|
dwc3_ep0_out_start(dwc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
switch (dwc->ep0state) {
|
|
|
|
case EP0_IDLE:
|
|
|
|
dwc3_ep0_inspect_setup(dwc, event);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EP0_IN_DATA_PHASE:
|
|
|
|
case EP0_OUT_DATA_PHASE:
|
|
|
|
dwc3_ep0_complete_data(dwc, event);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EP0_IN_STATUS_PHASE:
|
|
|
|
case EP0_OUT_STATUS_PHASE:
|
|
|
|
dwc3_ep0_complete_req(dwc, event);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EP0_IN_WAIT_NRDY:
|
|
|
|
case EP0_OUT_WAIT_NRDY:
|
|
|
|
case EP0_IN_WAIT_GADGET:
|
|
|
|
case EP0_OUT_WAIT_GADGET:
|
|
|
|
case EP0_UNCONNECTED:
|
|
|
|
case EP0_STALL:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
|
|
|
|
const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
switch (dwc->ep0state) {
|
|
|
|
case EP0_IN_WAIT_GADGET:
|
|
|
|
dwc->ep0state = EP0_IN_WAIT_NRDY;
|
|
|
|
break;
|
|
|
|
case EP0_OUT_WAIT_GADGET:
|
|
|
|
dwc->ep0state = EP0_OUT_WAIT_NRDY;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EP0_IN_WAIT_NRDY:
|
|
|
|
case EP0_OUT_WAIT_NRDY:
|
|
|
|
dwc3_ep0_do_setup_status(dwc, event);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case EP0_IDLE:
|
|
|
|
case EP0_IN_STATUS_PHASE:
|
|
|
|
case EP0_OUT_STATUS_PHASE:
|
|
|
|
case EP0_IN_DATA_PHASE:
|
|
|
|
case EP0_OUT_DATA_PHASE:
|
|
|
|
case EP0_UNCONNECTED:
|
|
|
|
case EP0_STALL:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void dwc3_ep0_interrupt(struct dwc3 *dwc,
|
|
|
|
const const struct dwc3_event_depevt *event)
|
|
|
|
{
|
|
|
|
u8 epnum = event->endpoint_number;
|
|
|
|
|
|
|
|
dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
|
|
|
|
dwc3_ep_event_string(event->endpoint_event),
|
|
|
|
epnum, (epnum & 1) ? "in" : "out",
|
|
|
|
dwc3_ep0_state_string(dwc->ep0state));
|
|
|
|
|
|
|
|
switch (event->endpoint_event) {
|
|
|
|
case DWC3_DEPEVT_XFERCOMPLETE:
|
|
|
|
dwc3_ep0_xfer_complete(dwc, event);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DWC3_DEPEVT_XFERNOTREADY:
|
|
|
|
dwc3_ep0_xfernotready(dwc, event);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DWC3_DEPEVT_XFERINPROGRESS:
|
|
|
|
case DWC3_DEPEVT_RXTXFIFOEVT:
|
|
|
|
case DWC3_DEPEVT_STREAMEVT:
|
|
|
|
case DWC3_DEPEVT_EPCMDCMPLT:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|