2008-01-30 12:30:55 +00:00
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#ifndef _ASM_X86_BITOPS_H
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#define _ASM_X86_BITOPS_H
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/*
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* Copyright 1992, Linus Torvalds.
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*/
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <asm/alternative.h>
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
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/* Technically wrong, but this avoids compilation errors on some gcc
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versions. */
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2008-03-23 08:01:45 +00:00
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#define ADDR "=m" (*(volatile long *)addr)
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#define BIT_ADDR "=m" (((volatile int *)addr)[nr >> 5])
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2008-01-30 12:30:55 +00:00
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#else
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#define ADDR "+m" (*(volatile long *) addr)
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2008-03-23 08:01:45 +00:00
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#define BIT_ADDR "+m" (((volatile int *)addr)[nr >> 5])
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2008-01-30 12:30:55 +00:00
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#endif
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2008-03-23 08:01:45 +00:00
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#define BASE_ADDR "m" (*(volatile int *)addr)
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2008-01-30 12:30:55 +00:00
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writing portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void set_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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2008-03-23 08:01:45 +00:00
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asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory");
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2008-01-30 12:30:55 +00:00
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}
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void __set_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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asm volatile("bts %1,%0"
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: ADDR
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: "Ir" (nr) : "memory");
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void clear_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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2008-03-23 08:01:45 +00:00
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asm volatile(LOCK_PREFIX "btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
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2008-01-30 12:30:55 +00:00
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}
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/*
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* clear_bit_unlock - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and implies release semantics before the memory
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* operation. It can be used for an unlock.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void clear_bit_unlock(unsigned nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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barrier();
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clear_bit(nr, addr);
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}
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2008-01-30 12:31:31 +00:00
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static inline void __clear_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
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asm volatile("btr %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
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2008-01-30 12:30:55 +00:00
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}
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/*
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* __clear_bit_unlock - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* __clear_bit() is non-atomic and implies release semantics before the memory
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* operation. It can be used for an unlock if no other CPUs can concurrently
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* modify other bits in the word.
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*
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* No memory barrier is required here, because x86 cannot reorder stores past
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* older loads. Same principle as spin_unlock.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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barrier();
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__clear_bit(nr, addr);
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}
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void __change_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
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asm volatile("btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
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2008-01-30 12:30:55 +00:00
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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2008-01-30 12:31:31 +00:00
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static inline void change_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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2008-03-23 08:01:45 +00:00
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asm volatile(LOCK_PREFIX "btc %1,%2" : BIT_ADDR : "Ir" (nr), BASE_ADDR);
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2008-01-30 12:30:55 +00:00
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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2008-01-30 12:31:31 +00:00
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static inline int test_and_set_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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int oldbit;
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asm volatile(LOCK_PREFIX "bts %2,%1\n\t"
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2008-03-23 08:01:45 +00:00
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"sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
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2008-01-30 12:30:55 +00:00
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return oldbit;
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}
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/**
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* test_and_set_bit_lock - Set a bit and return its old value for lock
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This is the same as test_and_set_bit on x86.
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*/
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2008-01-30 12:31:31 +00:00
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static inline int test_and_set_bit_lock(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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return test_and_set_bit(nr, addr);
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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2008-01-30 12:31:31 +00:00
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static inline int __test_and_set_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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int oldbit;
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|
x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
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asm volatile("bts %2,%3\n\t"
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"sbb %0,%0"
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2008-03-23 08:01:45 +00:00
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: "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
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2008-01-30 12:30:55 +00:00
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return oldbit;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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2008-01-30 12:31:31 +00:00
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static inline int test_and_clear_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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int oldbit;
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asm volatile(LOCK_PREFIX "btr %2,%1\n\t"
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"sbb %0,%0"
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2008-03-23 08:01:45 +00:00
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: "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
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2008-01-30 12:30:55 +00:00
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return oldbit;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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2008-01-30 12:31:31 +00:00
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static inline int __test_and_clear_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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int oldbit;
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|
x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
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asm volatile("btr %2,%3\n\t"
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2008-01-30 12:30:55 +00:00
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"sbb %0,%0"
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2008-03-23 08:01:45 +00:00
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: "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
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2008-01-30 12:30:55 +00:00
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return oldbit;
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}
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/* WARNING: non atomic and it can be reordered! */
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2008-01-30 12:31:31 +00:00
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static inline int __test_and_change_bit(int nr, volatile void *addr)
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2008-01-30 12:30:55 +00:00
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{
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int oldbit;
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|
|
|
|
x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
|
|
|
asm volatile("btc %2,%3\n\t"
|
2008-01-30 12:30:55 +00:00
|
|
|
"sbb %0,%0"
|
2008-03-23 08:01:45 +00:00
|
|
|
: "=r" (oldbit), BIT_ADDR : "Ir" (nr), BASE_ADDR);
|
2008-01-30 12:30:55 +00:00
|
|
|
|
|
|
|
return oldbit;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* test_and_change_bit - Change a bit and return its old value
|
|
|
|
* @nr: Bit to change
|
|
|
|
* @addr: Address to count from
|
|
|
|
*
|
|
|
|
* This operation is atomic and cannot be reordered.
|
|
|
|
* It also implies a memory barrier.
|
|
|
|
*/
|
2008-01-30 12:31:31 +00:00
|
|
|
static inline int test_and_change_bit(int nr, volatile void *addr)
|
2008-01-30 12:30:55 +00:00
|
|
|
{
|
|
|
|
int oldbit;
|
|
|
|
|
|
|
|
asm volatile(LOCK_PREFIX "btc %2,%1\n\t"
|
|
|
|
"sbb %0,%0"
|
2008-03-23 08:01:45 +00:00
|
|
|
: "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
|
2008-01-30 12:30:55 +00:00
|
|
|
|
|
|
|
return oldbit;
|
|
|
|
}
|
|
|
|
|
2008-01-30 12:31:31 +00:00
|
|
|
static inline int constant_test_bit(int nr, const volatile void *addr)
|
2008-01-30 12:30:55 +00:00
|
|
|
{
|
2008-01-30 12:31:31 +00:00
|
|
|
return ((1UL << (nr % BITS_PER_LONG)) &
|
|
|
|
(((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
|
2008-01-30 12:30:55 +00:00
|
|
|
}
|
|
|
|
|
2008-01-30 12:31:31 +00:00
|
|
|
static inline int variable_test_bit(int nr, volatile const void *addr)
|
2008-01-30 12:30:55 +00:00
|
|
|
{
|
|
|
|
int oldbit;
|
|
|
|
|
x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
|
|
|
asm volatile("bt %2,%3\n\t"
|
2008-01-30 12:30:55 +00:00
|
|
|
"sbb %0,%0"
|
|
|
|
: "=r" (oldbit)
|
x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
|
|
|
: "m" (((volatile const int *)addr)[nr >> 5]),
|
|
|
|
"Ir" (nr), BASE_ADDR);
|
2008-01-30 12:30:55 +00:00
|
|
|
|
|
|
|
return oldbit;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if 0 /* Fool kernel-doc since it doesn't do macros yet */
|
|
|
|
/**
|
|
|
|
* test_bit - Determine whether a bit is set
|
|
|
|
* @nr: bit number to test
|
|
|
|
* @addr: Address to start counting from
|
|
|
|
*/
|
|
|
|
static int test_bit(int nr, const volatile unsigned long *addr);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define test_bit(nr,addr) \
|
|
|
|
(__builtin_constant_p(nr) ? \
|
|
|
|
constant_test_bit((nr),(addr)) : \
|
|
|
|
variable_test_bit((nr),(addr)))
|
|
|
|
|
x86: bitops asm constraint fixes
This (simplified) piece of code didn't behave as expected due to
incorrect constraints in some of the bitops functions, when
X86_FEATURE_xxx is referring to other than the first long:
int test(struct cpuinfo_x86 *c) {
if (cpu_has(c, X86_FEATURE_xxx))
clear_cpu_cap(c, X86_FEATURE_xxx);
return cpu_has(c, X86_FEATURE_xxx);
}
I'd really like understand, though, what the policy of (not) having a
"memory" clobber in these operations is - currently, this appears to
be totally inconsistent. Also, many comments of the non-atomic
functions say those may also be re-ordered - this contradicts the use
of "asm volatile" in there, which again I'd like to understand.
As much as all of these, using 'int' for the 'nr' parameter and
'void *' for the 'addr' one is in conflict with
Documentation/atomic_ops.txt, especially because bt{,c,r,s} indeed
take the bit index as signed (which hence would really need special
precaution) and access the full 32 bits (if 'unsigned long' was used
properly here, 64 bits for x86-64) pointed at, so invalid uses like
referencing a 'char' array cannot currently be caught.
Finally, the code with and without this patch relies heavily on the
-fno-strict-aliasing compiler switch and I'm not certain this really
is a good idea.
In the light of all of this I'm sending this as RFC, as fixing the
above might warrant a much bigger patch...
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-13 09:08:51 +00:00
|
|
|
#undef BASE_ADDR
|
|
|
|
#undef BIT_ADDR
|
2008-01-30 12:30:55 +00:00
|
|
|
#undef ADDR
|
|
|
|
|
2007-10-11 09:20:03 +00:00
|
|
|
#ifdef CONFIG_X86_32
|
|
|
|
# include "bitops_32.h"
|
|
|
|
#else
|
|
|
|
# include "bitops_64.h"
|
|
|
|
#endif
|
2008-01-30 12:30:55 +00:00
|
|
|
|
|
|
|
#endif /* _ASM_X86_BITOPS_H */
|