2008-07-24 09:27:36 +00:00
|
|
|
/*
|
|
|
|
* MUSB OTG driver - support for Mentor's DMA controller
|
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*
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|
* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2007 by Texas Instruments
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*
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|
* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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|
* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/device.h>
|
|
|
|
#include <linux/interrupt.h>
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|
|
|
#include <linux/platform_device.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
|
|
|
#include <linux/slab.h>
|
2008-07-24 09:27:36 +00:00
|
|
|
#include "musb_core.h"
|
2008-12-02 19:33:47 +00:00
|
|
|
#include "musbhsdma.h"
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
static int dma_controller_start(struct dma_controller *c)
|
|
|
|
{
|
|
|
|
/* nothing to do */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
static void dma_channel_release(struct dma_channel *channel);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
static int dma_controller_stop(struct dma_controller *c)
|
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_controller *controller = container_of(c,
|
|
|
|
struct musb_dma_controller, controller);
|
|
|
|
struct musb *musb = controller->private_data;
|
|
|
|
struct dma_channel *channel;
|
|
|
|
u8 bit;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
if (controller->used_channels != 0) {
|
2008-07-24 09:27:36 +00:00
|
|
|
dev_err(musb->controller,
|
|
|
|
"Stopping DMA controller while channel active\n");
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
|
|
|
|
if (controller->used_channels & (1 << bit)) {
|
|
|
|
channel = &controller->channel[bit].channel;
|
|
|
|
dma_channel_release(channel);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
if (!controller->used_channels)
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-09-11 08:53:24 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
|
|
|
|
struct musb_hw_ep *hw_ep, u8 transmit)
|
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_controller *controller = container_of(c,
|
|
|
|
struct musb_dma_controller, controller);
|
|
|
|
struct musb_dma_channel *musb_channel = NULL;
|
|
|
|
struct dma_channel *channel = NULL;
|
|
|
|
u8 bit;
|
|
|
|
|
|
|
|
for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
|
|
|
|
if (!(controller->used_channels & (1 << bit))) {
|
|
|
|
controller->used_channels |= (1 << bit);
|
|
|
|
musb_channel = &(controller->channel[bit]);
|
|
|
|
musb_channel->controller = controller;
|
|
|
|
musb_channel->idx = bit;
|
|
|
|
musb_channel->epnum = hw_ep->epnum;
|
|
|
|
musb_channel->transmit = transmit;
|
|
|
|
channel = &(musb_channel->channel);
|
|
|
|
channel->private_data = musb_channel;
|
|
|
|
channel->status = MUSB_DMA_STATUS_FREE;
|
|
|
|
channel->max_len = 0x10000;
|
2008-07-24 09:27:36 +00:00
|
|
|
/* Tx => mode 1; Rx => mode 0 */
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->desired_mode = transmit;
|
|
|
|
channel->actual_len = 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2008-09-11 08:53:24 +00:00
|
|
|
|
|
|
|
return channel;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
static void dma_channel_release(struct dma_channel *channel)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_channel *musb_channel = channel->private_data;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->actual_len = 0;
|
|
|
|
musb_channel->start_addr = 0;
|
|
|
|
musb_channel->len = 0;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
musb_channel->controller->used_channels &=
|
|
|
|
~(1 << musb_channel->idx);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->status = MUSB_DMA_STATUS_UNKNOWN;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
static void configure_channel(struct dma_channel *channel,
|
2008-07-24 09:27:36 +00:00
|
|
|
u16 packet_sz, u8 mode,
|
|
|
|
dma_addr_t dma_addr, u32 len)
|
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_channel *musb_channel = channel->private_data;
|
|
|
|
struct musb_dma_controller *controller = musb_channel->controller;
|
|
|
|
void __iomem *mbase = controller->base;
|
|
|
|
u8 bchannel = musb_channel->idx;
|
2008-07-24 09:27:36 +00:00
|
|
|
u16 csr = 0;
|
|
|
|
|
|
|
|
DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
|
2008-09-11 08:53:24 +00:00
|
|
|
channel, packet_sz, dma_addr, len, mode);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
if (mode) {
|
|
|
|
csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
|
|
|
|
BUG_ON(len < packet_sz);
|
|
|
|
}
|
2010-06-24 17:37:09 +00:00
|
|
|
csr |= MUSB_HSDMA_BURSTMODE_INCR16
|
|
|
|
<< MUSB_HSDMA_BURSTMODE_SHIFT;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
|
2008-07-24 09:27:36 +00:00
|
|
|
| (1 << MUSB_HSDMA_ENABLE_SHIFT)
|
|
|
|
| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
|
2008-09-11 08:53:24 +00:00
|
|
|
| (musb_channel->transmit
|
2008-07-24 09:27:36 +00:00
|
|
|
? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
|
|
|
|
: 0);
|
|
|
|
|
|
|
|
/* address/count */
|
2008-12-02 19:33:47 +00:00
|
|
|
musb_write_hsdma_addr(mbase, bchannel, dma_addr);
|
|
|
|
musb_write_hsdma_count(mbase, bchannel, len);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* control (this should start things) */
|
|
|
|
musb_writew(mbase,
|
2008-09-11 08:53:24 +00:00
|
|
|
MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
|
2008-07-24 09:27:36 +00:00
|
|
|
csr);
|
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
static int dma_channel_program(struct dma_channel *channel,
|
2008-07-24 09:27:36 +00:00
|
|
|
u16 packet_sz, u8 mode,
|
|
|
|
dma_addr_t dma_addr, u32 len)
|
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_channel *musb_channel = channel->private_data;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
|
2008-09-11 08:53:24 +00:00
|
|
|
musb_channel->epnum,
|
|
|
|
musb_channel->transmit ? "Tx" : "Rx",
|
2008-07-24 09:27:36 +00:00
|
|
|
packet_sz, dma_addr, len, mode);
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
|
|
|
|
channel->status == MUSB_DMA_STATUS_BUSY);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->actual_len = 0;
|
|
|
|
musb_channel->start_addr = dma_addr;
|
|
|
|
musb_channel->len = len;
|
|
|
|
musb_channel->max_packet_sz = packet_sz;
|
|
|
|
channel->status = MUSB_DMA_STATUS_BUSY;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2010-07-08 11:04:55 +00:00
|
|
|
configure_channel(channel, packet_sz, mode, dma_addr, len);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
static int dma_channel_abort(struct dma_channel *channel)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_channel *musb_channel = channel->private_data;
|
|
|
|
void __iomem *mbase = musb_channel->controller->base;
|
|
|
|
|
|
|
|
u8 bchannel = musb_channel->idx;
|
2009-03-27 01:27:47 +00:00
|
|
|
int offset;
|
2008-07-24 09:27:36 +00:00
|
|
|
u16 csr;
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
if (channel->status == MUSB_DMA_STATUS_BUSY) {
|
|
|
|
if (musb_channel->transmit) {
|
2009-03-27 01:27:47 +00:00
|
|
|
offset = MUSB_EP_OFFSET(musb_channel->epnum,
|
|
|
|
MUSB_TXCSR);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The programming guide says that we must clear
|
|
|
|
* the DMAENAB bit before the DMAMODE bit...
|
|
|
|
*/
|
|
|
|
csr = musb_readw(mbase, offset);
|
|
|
|
csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
|
|
|
|
musb_writew(mbase, offset, csr);
|
|
|
|
csr &= ~MUSB_TXCSR_DMAMODE;
|
|
|
|
musb_writew(mbase, offset, csr);
|
2008-07-24 09:27:36 +00:00
|
|
|
} else {
|
2009-03-27 01:27:47 +00:00
|
|
|
offset = MUSB_EP_OFFSET(musb_channel->epnum,
|
|
|
|
MUSB_RXCSR);
|
|
|
|
|
|
|
|
csr = musb_readw(mbase, offset);
|
2008-07-24 09:27:36 +00:00
|
|
|
csr &= ~(MUSB_RXCSR_AUTOCLEAR |
|
|
|
|
MUSB_RXCSR_DMAENAB |
|
|
|
|
MUSB_RXCSR_DMAMODE);
|
2009-03-27 01:27:47 +00:00
|
|
|
musb_writew(mbase, offset, csr);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
musb_writew(mbase,
|
2008-09-11 08:53:24 +00:00
|
|
|
MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
|
2008-07-24 09:27:36 +00:00
|
|
|
0);
|
2008-12-02 19:33:47 +00:00
|
|
|
musb_write_hsdma_addr(mbase, bchannel, 0);
|
|
|
|
musb_write_hsdma_count(mbase, bchannel, 0);
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->status = MUSB_DMA_STATUS_FREE;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
2008-09-11 08:53:24 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t dma_controller_irq(int irq, void *private_data)
|
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_controller *controller = private_data;
|
|
|
|
struct musb *musb = controller->private_data;
|
|
|
|
struct musb_dma_channel *musb_channel;
|
|
|
|
struct dma_channel *channel;
|
|
|
|
|
|
|
|
void __iomem *mbase = controller->base;
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
irqreturn_t retval = IRQ_NONE;
|
2008-09-11 08:53:24 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
unsigned long flags;
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
u8 bchannel;
|
|
|
|
u8 int_hsdma;
|
|
|
|
|
2009-12-28 11:40:36 +00:00
|
|
|
u32 addr, count;
|
2008-09-11 08:53:24 +00:00
|
|
|
u16 csr;
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
spin_lock_irqsave(&musb->lock, flags);
|
|
|
|
|
|
|
|
int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
|
|
|
|
|
2009-11-16 10:49:26 +00:00
|
|
|
#ifdef CONFIG_BLACKFIN
|
|
|
|
/* Clear DMA interrupt flags */
|
|
|
|
musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
|
|
|
|
#endif
|
|
|
|
|
2009-12-28 11:40:36 +00:00
|
|
|
if (!int_hsdma) {
|
|
|
|
DBG(2, "spurious DMA irq\n");
|
|
|
|
|
|
|
|
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
|
|
|
|
musb_channel = (struct musb_dma_channel *)
|
|
|
|
&(controller->channel[bchannel]);
|
|
|
|
channel = &musb_channel->channel;
|
|
|
|
if (channel->status == MUSB_DMA_STATUS_BUSY) {
|
|
|
|
count = musb_read_hsdma_count(mbase, bchannel);
|
|
|
|
|
|
|
|
if (count == 0)
|
|
|
|
int_hsdma |= (1 << bchannel);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
|
|
|
|
|
|
|
|
if (!int_hsdma)
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
|
|
|
|
if (int_hsdma & (1 << bchannel)) {
|
|
|
|
musb_channel = (struct musb_dma_channel *)
|
|
|
|
&(controller->channel[bchannel]);
|
|
|
|
channel = &musb_channel->channel;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
csr = musb_readw(mbase,
|
2008-09-11 08:53:24 +00:00
|
|
|
MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
|
2008-07-24 09:27:36 +00:00
|
|
|
MUSB_HSDMA_CONTROL));
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
|
|
|
|
musb_channel->channel.status =
|
2008-07-24 09:27:36 +00:00
|
|
|
MUSB_DMA_STATUS_BUS_ABORT;
|
2008-09-11 08:53:24 +00:00
|
|
|
} else {
|
2008-07-24 09:27:36 +00:00
|
|
|
u8 devctl;
|
|
|
|
|
2008-12-02 19:33:47 +00:00
|
|
|
addr = musb_read_hsdma_addr(mbase,
|
|
|
|
bchannel);
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->actual_len = addr
|
|
|
|
- musb_channel->start_addr;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2009-11-16 10:49:29 +00:00
|
|
|
DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
|
2008-09-11 08:53:24 +00:00
|
|
|
channel, musb_channel->start_addr,
|
|
|
|
addr, channel->actual_len,
|
|
|
|
musb_channel->len,
|
|
|
|
(channel->actual_len
|
|
|
|
< musb_channel->len) ?
|
2008-07-24 09:27:36 +00:00
|
|
|
"=> reconfig 0" : "=> complete");
|
|
|
|
|
|
|
|
devctl = musb_readb(mbase, MUSB_DEVCTL);
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
channel->status = MUSB_DMA_STATUS_FREE;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
/* completed */
|
|
|
|
if ((devctl & MUSB_DEVCTL_HM)
|
2008-09-11 08:53:24 +00:00
|
|
|
&& (musb_channel->transmit)
|
|
|
|
&& ((channel->desired_mode == 0)
|
|
|
|
|| (channel->actual_len &
|
|
|
|
(musb_channel->max_packet_sz - 1)))
|
2009-03-27 01:27:47 +00:00
|
|
|
) {
|
|
|
|
u8 epnum = musb_channel->epnum;
|
|
|
|
int offset = MUSB_EP_OFFSET(epnum,
|
|
|
|
MUSB_TXCSR);
|
|
|
|
u16 txcsr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The programming guide says that we
|
|
|
|
* must clear DMAENAB before DMAMODE.
|
|
|
|
*/
|
|
|
|
musb_ep_select(mbase, epnum);
|
|
|
|
txcsr = musb_readw(mbase, offset);
|
|
|
|
txcsr &= ~(MUSB_TXCSR_DMAENAB
|
|
|
|
| MUSB_TXCSR_AUTOSET);
|
|
|
|
musb_writew(mbase, offset, txcsr);
|
2008-07-24 09:27:36 +00:00
|
|
|
/* Send out the packet */
|
2009-03-27 01:27:47 +00:00
|
|
|
txcsr &= ~MUSB_TXCSR_DMAMODE;
|
|
|
|
txcsr |= MUSB_TXCSR_TXPKTRDY;
|
|
|
|
musb_writew(mbase, offset, txcsr);
|
2008-09-11 08:53:24 +00:00
|
|
|
}
|
USB: musb: bugfixes for multi-packet TXDMA support
We really want to use DMA mode 1 for all multi-packet transfers;
that's one IRQ on DMA completion, instead of one per packet.
There is an important issue with such transfers, especially on
the host side: when such transfers end with a full-size packet,
we must defer musb_dma_completion() calls until the FIFO empties.
Else we report URB completions too soon, and may clobber data in
the FIFO fifo when writing the next packet (losing data).
The Inventra DMA support uses DMA mode 1, but it ignores that
issue. The CPPI DMA support uses mode 0, but doesn't handle
its TXPKTRDY interrupts quite right either; it can get stale
"packet ready" interrupts, and report transfer completion too
early using slightly different code paths, also losing data.
So I'm solving it in a generic way -- by adding a sort of the
"interrupt filter" into musb_host_tx(), catching these cases
where a DMA completion IRQ doesn't suffice and removing some
needlessly controller-specific logic. When a TXDMA interrupt
happens and DMA request mode 1 is active, that filter resets
to mode 0 and defers URB completion processing until TXPKTRDY,
unless the FIFO is already empty. Related filtering logic in
Inventra and CPPI code gets removed.
Since it should be competely safe now to use the DMA request
mode 1 for host side transfers with the CPPI DMA controller,
set it in musb_h_tx_dma_start() ... now renamed (and shared).
[ dbrownell@users.sourceforge.net: don't introduce more
CamElCase; use more concise explanations ]
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-03-27 01:26:40 +00:00
|
|
|
musb_dma_completion(musb, musb_channel->epnum,
|
|
|
|
musb_channel->transmit);
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-12-02 19:33:47 +00:00
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
retval = IRQ_HANDLED;
|
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dma_controller_destroy(struct dma_controller *c)
|
|
|
|
{
|
2008-09-11 08:53:24 +00:00
|
|
|
struct musb_dma_controller *controller = container_of(c,
|
|
|
|
struct musb_dma_controller, controller);
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
if (!controller)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (controller->irq)
|
|
|
|
free_irq(controller->irq, c);
|
|
|
|
|
|
|
|
kfree(controller);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct dma_controller *__init
|
2008-09-11 08:53:24 +00:00
|
|
|
dma_controller_create(struct musb *musb, void __iomem *base)
|
2008-07-24 09:27:36 +00:00
|
|
|
{
|
|
|
|
struct musb_dma_controller *controller;
|
|
|
|
struct device *dev = musb->controller;
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
int irq = platform_get_irq(pdev, 1);
|
|
|
|
|
|
|
|
if (irq == 0) {
|
|
|
|
dev_err(dev, "No DMA interrupt line!\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
controller = kzalloc(sizeof(*controller), GFP_KERNEL);
|
2008-07-24 09:27:36 +00:00
|
|
|
if (!controller)
|
|
|
|
return NULL;
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
controller->channel_count = MUSB_HSDMA_CHANNELS;
|
|
|
|
controller->private_data = musb;
|
|
|
|
controller->base = base;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
controller->controller.start = dma_controller_start;
|
|
|
|
controller->controller.stop = dma_controller_stop;
|
|
|
|
controller->controller.channel_alloc = dma_channel_allocate;
|
|
|
|
controller->controller.channel_release = dma_channel_release;
|
|
|
|
controller->controller.channel_program = dma_channel_program;
|
|
|
|
controller->controller.channel_abort = dma_channel_abort;
|
2008-07-24 09:27:36 +00:00
|
|
|
|
|
|
|
if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
|
2008-11-07 00:52:53 +00:00
|
|
|
dev_name(musb->controller), &controller->controller)) {
|
2008-07-24 09:27:36 +00:00
|
|
|
dev_err(dev, "request_irq %d failed!\n", irq);
|
2008-09-11 08:53:24 +00:00
|
|
|
dma_controller_destroy(&controller->controller);
|
|
|
|
|
2008-07-24 09:27:36 +00:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
controller->irq = irq;
|
|
|
|
|
2008-09-11 08:53:24 +00:00
|
|
|
return &controller->controller;
|
2008-07-24 09:27:36 +00:00
|
|
|
}
|