2010-10-06 08:25:55 +00:00
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/*
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* drivers/dma/imx-dma.c
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*
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* This file contains a driver for the Freescale i.MX DMA engine
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* found on i.MX1/21/27
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*
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* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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2012-03-02 08:28:47 +00:00
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* Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
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2010-10-06 08:25:55 +00:00
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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2011-08-30 07:08:24 +00:00
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#include <linux/module.h>
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2010-10-06 08:25:55 +00:00
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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2012-03-22 13:54:01 +00:00
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#include <linux/clk.h>
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2010-10-06 08:25:55 +00:00
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#include <linux/dmaengine.h>
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2012-03-09 09:25:25 +00:00
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#include <linux/module.h>
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2010-10-06 08:25:55 +00:00
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#include <asm/irq.h>
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2012-03-22 13:54:01 +00:00
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#include <mach/dma.h>
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2010-10-06 08:25:55 +00:00
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#include <mach/hardware.h>
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2012-03-06 22:34:26 +00:00
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#include "dmaengine.h"
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2012-03-02 08:28:47 +00:00
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#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
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2012-03-22 13:54:01 +00:00
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#define IMX_DMA_CHANNELS 16
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#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
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#define IMX_DMA_MEMSIZE_32 (0 << 4)
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#define IMX_DMA_MEMSIZE_8 (1 << 4)
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#define IMX_DMA_MEMSIZE_16 (2 << 4)
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#define IMX_DMA_TYPE_LINEAR (0 << 10)
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#define IMX_DMA_TYPE_2D (1 << 10)
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#define IMX_DMA_TYPE_FIFO (2 << 10)
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#define IMX_DMA_ERR_BURST (1 << 0)
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#define IMX_DMA_ERR_REQUEST (1 << 1)
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#define IMX_DMA_ERR_TRANSFER (1 << 2)
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#define IMX_DMA_ERR_BUFFER (1 << 3)
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#define IMX_DMA_ERR_TIMEOUT (1 << 4)
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#define DMA_DCR 0x00 /* Control Register */
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#define DMA_DISR 0x04 /* Interrupt status Register */
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#define DMA_DIMR 0x08 /* Interrupt mask Register */
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#define DMA_DBTOSR 0x0c /* Burst timeout status Register */
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#define DMA_DRTOSR 0x10 /* Request timeout Register */
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#define DMA_DSESR 0x14 /* Transfer Error Status Register */
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#define DMA_DBOSR 0x18 /* Buffer overflow status Register */
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#define DMA_DBTOCR 0x1c /* Burst timeout control Register */
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#define DMA_WSRA 0x40 /* W-Size Register A */
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#define DMA_XSRA 0x44 /* X-Size Register A */
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#define DMA_YSRA 0x48 /* Y-Size Register A */
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#define DMA_WSRB 0x4c /* W-Size Register B */
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#define DMA_XSRB 0x50 /* X-Size Register B */
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#define DMA_YSRB 0x54 /* Y-Size Register B */
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#define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
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#define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
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#define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
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#define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
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#define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
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#define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
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#define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
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#define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
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#define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
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#define DCR_DRST (1<<1)
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#define DCR_DEN (1<<0)
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#define DBTOCR_EN (1<<15)
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#define DBTOCR_CNT(x) ((x) & 0x7fff)
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#define CNTR_CNT(x) ((x) & 0xffffff)
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#define CCR_ACRPT (1<<14)
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#define CCR_DMOD_LINEAR (0x0 << 12)
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#define CCR_DMOD_2D (0x1 << 12)
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#define CCR_DMOD_FIFO (0x2 << 12)
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#define CCR_DMOD_EOBFIFO (0x3 << 12)
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#define CCR_SMOD_LINEAR (0x0 << 10)
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#define CCR_SMOD_2D (0x1 << 10)
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#define CCR_SMOD_FIFO (0x2 << 10)
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#define CCR_SMOD_EOBFIFO (0x3 << 10)
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#define CCR_MDIR_DEC (1<<9)
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#define CCR_MSEL_B (1<<8)
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#define CCR_DSIZ_32 (0x0 << 6)
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#define CCR_DSIZ_8 (0x1 << 6)
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#define CCR_DSIZ_16 (0x2 << 6)
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#define CCR_SSIZ_32 (0x0 << 4)
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#define CCR_SSIZ_8 (0x1 << 4)
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#define CCR_SSIZ_16 (0x2 << 4)
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#define CCR_REN (1<<3)
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#define CCR_RPT (1<<2)
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#define CCR_FRC (1<<1)
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#define CCR_CEN (1<<0)
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#define RTOR_EN (1<<15)
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#define RTOR_CLK (1<<14)
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#define RTOR_PSC (1<<13)
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2012-03-02 08:28:47 +00:00
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enum imxdma_prep_type {
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IMXDMA_DESC_MEMCPY,
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IMXDMA_DESC_INTERLEAVED,
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IMXDMA_DESC_SLAVE_SG,
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IMXDMA_DESC_CYCLIC,
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};
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2012-03-22 13:54:01 +00:00
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/*
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* struct imxdma_channel_internal - i.MX specific DMA extension
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* @name: name specified by DMA client
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* @irq_handler: client callback for end of transfer
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* @err_handler: client callback for error condition
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* @data: clients context data for callbacks
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* @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
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* @sg: pointer to the actual read/written chunk for scatter-gather emulation
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* @resbytes: total residual number of bytes to transfer
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* (it can be lower or same as sum of SG mapped chunk sizes)
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* @sgcount: number of chunks to be read/written
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*
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* Structure is used for IMX DMA processing. It would be probably good
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* @struct dma_struct in the future for external interfacing and use
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* @struct imxdma_channel_internal only as extension to it.
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*/
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struct imxdma_channel_internal {
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struct timer_list watchdog;
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int hw_chaining;
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};
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2012-03-02 08:28:47 +00:00
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struct imxdma_desc {
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struct list_head node;
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struct dma_async_tx_descriptor desc;
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enum dma_status status;
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dma_addr_t src;
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dma_addr_t dest;
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size_t len;
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2012-03-22 13:54:03 +00:00
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enum dma_transfer_direction direction;
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2012-03-02 08:28:47 +00:00
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enum imxdma_prep_type type;
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/* For memcpy and interleaved */
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unsigned int config_port;
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unsigned int config_mem;
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/* For interleaved transfers */
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unsigned int x;
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unsigned int y;
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unsigned int w;
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/* For slave sg and cyclic */
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struct scatterlist *sg;
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unsigned int sgcount;
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};
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2010-10-06 08:25:55 +00:00
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struct imxdma_channel {
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2012-03-22 13:54:01 +00:00
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struct imxdma_channel_internal internal;
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2010-10-06 08:25:55 +00:00
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struct imxdma_engine *imxdma;
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unsigned int channel;
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2012-03-02 08:28:47 +00:00
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struct tasklet_struct dma_tasklet;
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struct list_head ld_free;
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struct list_head ld_queue;
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struct list_head ld_active;
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int descs_allocated;
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2010-10-06 08:25:55 +00:00
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enum dma_slave_buswidth word_size;
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dma_addr_t per_address;
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u32 watermark_level;
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struct dma_chan chan;
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spinlock_t lock;
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struct dma_async_tx_descriptor desc;
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enum dma_status status;
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int dma_request;
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struct scatterlist *sg_list;
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2012-03-22 13:54:06 +00:00
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u32 ccr_from_device;
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u32 ccr_to_device;
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2010-10-06 08:25:55 +00:00
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};
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struct imxdma_engine {
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struct device *dev;
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2011-01-12 12:14:37 +00:00
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struct device_dma_parameters dma_parms;
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2010-10-06 08:25:55 +00:00
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struct dma_device dma_device;
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2012-03-22 13:54:01 +00:00
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struct imxdma_channel channel[IMX_DMA_CHANNELS];
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2010-10-06 08:25:55 +00:00
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};
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static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct imxdma_channel, chan);
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}
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2012-03-02 08:28:47 +00:00
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static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
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2010-10-06 08:25:55 +00:00
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{
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2012-03-02 08:28:47 +00:00
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struct imxdma_desc *desc;
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if (!list_empty(&imxdmac->ld_active)) {
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desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
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node);
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if (desc->type == IMXDMA_DESC_CYCLIC)
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return true;
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}
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return false;
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2010-10-06 08:25:55 +00:00
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}
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2012-03-22 13:54:01 +00:00
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/* TODO: put this inside any struct */
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static void __iomem *imx_dmav1_baseaddr;
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static struct clk *dma_clk;
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static void imx_dmav1_writel(unsigned val, unsigned offset)
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{
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__raw_writel(val, imx_dmav1_baseaddr + offset);
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}
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static unsigned imx_dmav1_readl(unsigned offset)
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2010-10-06 08:25:55 +00:00
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{
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2012-03-22 13:54:01 +00:00
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return __raw_readl(imx_dmav1_baseaddr + offset);
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}
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2010-10-06 08:25:55 +00:00
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2012-03-22 13:54:01 +00:00
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static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
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{
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if (cpu_is_mx27())
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return imxdma->hw_chaining;
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else
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return 0;
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}
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/*
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* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
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*/
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2012-03-22 13:54:03 +00:00
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static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
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2012-03-22 13:54:01 +00:00
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{
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2012-03-22 13:54:03 +00:00
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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2012-03-22 13:54:01 +00:00
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unsigned long now;
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2012-03-22 13:54:09 +00:00
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now = min(d->len, sg->length);
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if (d->len != IMX_DMA_LENGTH_LOOP)
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d->len -= now;
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2012-03-22 13:54:01 +00:00
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2012-03-22 13:54:03 +00:00
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if (d->direction == DMA_DEV_TO_MEM)
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2012-03-22 13:54:01 +00:00
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imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
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else
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imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(now, DMA_CNTR(imxdmac->channel));
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pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
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"size 0x%08x\n", imxdmac->channel,
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imx_dmav1_readl(DMA_DAR(imxdmac->channel)),
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imx_dmav1_readl(DMA_SAR(imxdmac->channel)),
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imx_dmav1_readl(DMA_CNTR(imxdmac->channel)));
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return now;
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}
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2012-03-22 13:54:03 +00:00
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static void imxdma_enable_hw(struct imxdma_desc *d)
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2012-03-22 13:54:01 +00:00
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{
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2012-03-22 13:54:03 +00:00
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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2012-03-22 13:54:01 +00:00
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int channel = imxdmac->channel;
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unsigned long flags;
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pr_debug("imxdma%d: imx_dma_enable\n", channel);
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local_irq_save(flags);
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imx_dmav1_writel(1 << channel, DMA_DISR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
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CCR_ACRPT, DMA_CCR(channel));
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if ((cpu_is_mx21() || cpu_is_mx27()) &&
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2012-03-22 13:54:07 +00:00
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d->sg && imxdma_hw_chain(&imxdmac->internal)) {
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d->sg = sg_next(d->sg);
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if (d->sg) {
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2012-03-22 13:54:01 +00:00
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u32 tmp;
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2012-03-22 13:54:07 +00:00
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imxdma_sg_next(d, d->sg);
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2012-03-22 13:54:01 +00:00
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tmp = imx_dmav1_readl(DMA_CCR(channel));
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imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
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DMA_CCR(channel));
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}
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}
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local_irq_restore(flags);
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}
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static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
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{
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int channel = imxdmac->channel;
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unsigned long flags;
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pr_debug("imxdma%d: imx_dma_disable\n", channel);
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if (imxdma_hw_chain(&imxdmac->internal))
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del_timer(&imxdmac->internal.watchdog);
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local_irq_save(flags);
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imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
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imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
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DMA_CCR(channel));
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imx_dmav1_writel(1 << channel, DMA_DISR);
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local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imxdma_watchdog(unsigned long data)
|
2010-10-06 08:25:55 +00:00
|
|
|
{
|
2012-03-22 13:54:01 +00:00
|
|
|
struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
|
|
|
|
int channel = imxdmac->channel;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
imx_dmav1_writel(0, DMA_CCR(channel));
|
|
|
|
|
|
|
|
/* Tasklet watchdog error handler */
|
2012-03-02 08:28:47 +00:00
|
|
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
2012-03-22 13:54:01 +00:00
|
|
|
pr_debug("imxdma%d: watchdog timeout!\n", imxdmac->channel);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct imxdma_engine *imxdma = dev_id;
|
|
|
|
struct imxdma_channel_internal *internal;
|
|
|
|
unsigned int err_mask;
|
|
|
|
int i, disr;
|
|
|
|
int errcode;
|
|
|
|
|
|
|
|
disr = imx_dmav1_readl(DMA_DISR);
|
|
|
|
|
|
|
|
err_mask = imx_dmav1_readl(DMA_DBTOSR) |
|
|
|
|
imx_dmav1_readl(DMA_DRTOSR) |
|
|
|
|
imx_dmav1_readl(DMA_DSESR) |
|
|
|
|
imx_dmav1_readl(DMA_DBOSR);
|
|
|
|
|
|
|
|
if (!err_mask)
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
|
|
imx_dmav1_writel(disr & err_mask, DMA_DISR);
|
|
|
|
|
|
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
|
|
if (!(err_mask & (1 << i)))
|
|
|
|
continue;
|
|
|
|
internal = &imxdma->channel[i].internal;
|
|
|
|
errcode = 0;
|
|
|
|
|
|
|
|
if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
|
|
|
|
imx_dmav1_writel(1 << i, DMA_DBTOSR);
|
|
|
|
errcode |= IMX_DMA_ERR_BURST;
|
|
|
|
}
|
|
|
|
if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
|
|
|
|
imx_dmav1_writel(1 << i, DMA_DRTOSR);
|
|
|
|
errcode |= IMX_DMA_ERR_REQUEST;
|
|
|
|
}
|
|
|
|
if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
|
|
|
|
imx_dmav1_writel(1 << i, DMA_DSESR);
|
|
|
|
errcode |= IMX_DMA_ERR_TRANSFER;
|
|
|
|
}
|
|
|
|
if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
|
|
|
|
imx_dmav1_writel(1 << i, DMA_DBOSR);
|
|
|
|
errcode |= IMX_DMA_ERR_BUFFER;
|
|
|
|
}
|
|
|
|
/* Tasklet error handler */
|
|
|
|
tasklet_schedule(&imxdma->channel[i].dma_tasklet);
|
|
|
|
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"DMA timeout on channel %d -%s%s%s%s\n", i,
|
|
|
|
errcode & IMX_DMA_ERR_BURST ? " burst" : "",
|
|
|
|
errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
|
|
|
|
errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
|
|
|
|
errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
|
|
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
|
2010-10-06 08:25:55 +00:00
|
|
|
{
|
2012-03-22 13:54:01 +00:00
|
|
|
struct imxdma_channel_internal *imxdma = &imxdmac->internal;
|
|
|
|
int chno = imxdmac->channel;
|
2012-03-22 13:54:03 +00:00
|
|
|
struct imxdma_desc *desc;
|
2012-03-22 13:54:01 +00:00
|
|
|
|
2012-03-22 13:54:07 +00:00
|
|
|
spin_lock(&imxdmac->lock);
|
|
|
|
if (list_empty(&imxdmac->ld_active)) {
|
|
|
|
spin_unlock(&imxdmac->lock);
|
|
|
|
goto out;
|
|
|
|
}
|
2012-03-22 13:54:03 +00:00
|
|
|
|
2012-03-22 13:54:07 +00:00
|
|
|
desc = list_first_entry(&imxdmac->ld_active,
|
|
|
|
struct imxdma_desc,
|
|
|
|
node);
|
|
|
|
spin_unlock(&imxdmac->lock);
|
2012-03-22 13:54:03 +00:00
|
|
|
|
2012-03-22 13:54:07 +00:00
|
|
|
if (desc->sg) {
|
|
|
|
u32 tmp;
|
|
|
|
desc->sg = sg_next(desc->sg);
|
2012-03-22 13:54:03 +00:00
|
|
|
|
2012-03-22 13:54:07 +00:00
|
|
|
if (desc->sg) {
|
|
|
|
imxdma_sg_next(desc, desc->sg);
|
2012-03-22 13:54:01 +00:00
|
|
|
|
|
|
|
tmp = imx_dmav1_readl(DMA_CCR(chno));
|
|
|
|
|
|
|
|
if (imxdma_hw_chain(imxdma)) {
|
|
|
|
/* FIXME: The timeout should probably be
|
|
|
|
* configurable
|
|
|
|
*/
|
|
|
|
mod_timer(&imxdma->watchdog,
|
|
|
|
jiffies + msecs_to_jiffies(500));
|
|
|
|
|
|
|
|
tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
|
|
|
|
imx_dmav1_writel(tmp, DMA_CCR(chno));
|
|
|
|
} else {
|
|
|
|
imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
|
|
|
|
tmp |= CCR_CEN;
|
|
|
|
}
|
|
|
|
|
|
|
|
imx_dmav1_writel(tmp, DMA_CCR(chno));
|
|
|
|
|
|
|
|
if (imxdma_chan_is_doing_cyclic(imxdmac))
|
|
|
|
/* Tasklet progression */
|
|
|
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (imxdma_hw_chain(imxdma)) {
|
|
|
|
del_timer(&imxdma->watchdog);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-03-22 13:54:03 +00:00
|
|
|
out:
|
2012-03-22 13:54:01 +00:00
|
|
|
imx_dmav1_writel(0, DMA_CCR(chno));
|
|
|
|
/* Tasklet irq */
|
2012-03-02 08:28:47 +00:00
|
|
|
tasklet_schedule(&imxdmac->dma_tasklet);
|
|
|
|
}
|
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct imxdma_engine *imxdma = dev_id;
|
|
|
|
struct imxdma_channel_internal *internal;
|
|
|
|
int i, disr;
|
|
|
|
|
|
|
|
if (cpu_is_mx21() || cpu_is_mx27())
|
|
|
|
imxdma_err_handler(irq, dev_id);
|
|
|
|
|
|
|
|
disr = imx_dmav1_readl(DMA_DISR);
|
|
|
|
|
|
|
|
pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
|
|
|
|
disr);
|
|
|
|
|
|
|
|
imx_dmav1_writel(disr, DMA_DISR);
|
|
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
|
|
|
if (disr & (1 << i)) {
|
|
|
|
internal = &imxdma->channel[i].internal;
|
|
|
|
dma_irq_handle_channel(&imxdma->channel[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
static int imxdma_xfer_desc(struct imxdma_desc *d)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
|
2012-03-22 13:54:04 +00:00
|
|
|
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
2012-03-02 08:28:47 +00:00
|
|
|
|
|
|
|
/* Configure and enable */
|
|
|
|
switch (d->type) {
|
|
|
|
case IMXDMA_DESC_MEMCPY:
|
2012-03-22 13:54:04 +00:00
|
|
|
imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
|
|
|
|
imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
|
|
|
|
imx_dmav1_writel(d->config_mem | (d->config_port << 2),
|
|
|
|
DMA_CCR(imxdmac->channel));
|
2012-03-22 13:54:01 +00:00
|
|
|
|
2012-03-22 13:54:04 +00:00
|
|
|
imx_dmav1_writel(d->len, DMA_CNTR(imxdmac->channel));
|
|
|
|
|
|
|
|
dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
|
|
|
|
"dma_length=%d\n", __func__, imxdmac->channel,
|
|
|
|
d->dest, d->src, d->len);
|
|
|
|
|
|
|
|
break;
|
2012-03-22 13:54:01 +00:00
|
|
|
/* Cyclic transfer is the same as slave_sg with special sg configuration. */
|
2012-03-02 08:28:47 +00:00
|
|
|
case IMXDMA_DESC_CYCLIC:
|
|
|
|
case IMXDMA_DESC_SLAVE_SG:
|
2012-03-22 13:54:06 +00:00
|
|
|
if (d->direction == DMA_DEV_TO_MEM) {
|
|
|
|
imx_dmav1_writel(imxdmac->per_address,
|
|
|
|
DMA_SAR(imxdmac->channel));
|
|
|
|
imx_dmav1_writel(imxdmac->ccr_from_device,
|
|
|
|
DMA_CCR(imxdmac->channel));
|
|
|
|
|
|
|
|
dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
|
|
|
|
"total length=%d dev_addr=0x%08x (dev2mem)\n",
|
|
|
|
__func__, imxdmac->channel, d->sg, d->sgcount,
|
|
|
|
d->len, imxdmac->per_address);
|
|
|
|
} else if (d->direction == DMA_MEM_TO_DEV) {
|
|
|
|
imx_dmav1_writel(imxdmac->per_address,
|
|
|
|
DMA_DAR(imxdmac->channel));
|
|
|
|
imx_dmav1_writel(imxdmac->ccr_to_device,
|
|
|
|
DMA_CCR(imxdmac->channel));
|
|
|
|
|
|
|
|
dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
|
|
|
|
"total length=%d dev_addr=0x%08x (mem2dev)\n",
|
|
|
|
__func__, imxdmac->channel, d->sg, d->sgcount,
|
|
|
|
d->len, imxdmac->per_address);
|
|
|
|
} else {
|
|
|
|
dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
|
|
|
|
__func__, imxdmac->channel);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
imxdma_sg_next(d, d->sg);
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2012-03-22 13:54:03 +00:00
|
|
|
imxdma_enable_hw(d);
|
2012-03-02 08:28:47 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imxdma_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = (void *)data;
|
|
|
|
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
|
|
|
struct imxdma_desc *desc;
|
|
|
|
|
|
|
|
spin_lock(&imxdmac->lock);
|
|
|
|
|
|
|
|
if (list_empty(&imxdmac->ld_active)) {
|
|
|
|
/* Someone might have called terminate all */
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
|
|
|
|
|
|
|
|
if (desc->desc.callback)
|
|
|
|
desc->desc.callback(desc->desc.callback_param);
|
|
|
|
|
2012-03-13 07:09:49 +00:00
|
|
|
dma_cookie_complete(&desc->desc);
|
2012-03-02 08:28:47 +00:00
|
|
|
|
|
|
|
/* If we are dealing with a cyclic descriptor keep it on ld_active */
|
|
|
|
if (imxdma_chan_is_doing_cyclic(imxdmac))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
|
|
|
|
|
|
|
|
if (!list_empty(&imxdmac->ld_queue)) {
|
|
|
|
desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
|
|
|
|
node);
|
|
|
|
list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
|
|
|
|
if (imxdma_xfer_desc(desc) < 0)
|
|
|
|
dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
|
|
|
|
__func__, imxdmac->channel);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
spin_unlock(&imxdmac->lock);
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
|
|
|
struct dma_slave_config *dmaengine_cfg = (void *)arg;
|
2012-03-02 08:28:47 +00:00
|
|
|
unsigned long flags;
|
2010-10-06 08:25:55 +00:00
|
|
|
unsigned int mode = 0;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case DMA_TERMINATE_ALL:
|
2012-03-22 13:54:01 +00:00
|
|
|
imxdma_disable_hw(imxdmac);
|
2012-03-02 08:28:47 +00:00
|
|
|
|
|
|
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
|
|
|
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
|
|
|
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
|
|
|
|
spin_unlock_irqrestore(&imxdmac->lock, flags);
|
2010-10-06 08:25:55 +00:00
|
|
|
return 0;
|
|
|
|
case DMA_SLAVE_CONFIG:
|
2011-10-13 17:04:23 +00:00
|
|
|
if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
|
2010-10-06 08:25:55 +00:00
|
|
|
imxdmac->per_address = dmaengine_cfg->src_addr;
|
|
|
|
imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
|
|
|
|
imxdmac->word_size = dmaengine_cfg->src_addr_width;
|
|
|
|
} else {
|
|
|
|
imxdmac->per_address = dmaengine_cfg->dst_addr;
|
|
|
|
imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
|
|
|
|
imxdmac->word_size = dmaengine_cfg->dst_addr_width;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (imxdmac->word_size) {
|
|
|
|
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
|
|
|
mode = IMX_DMA_MEMSIZE_8;
|
|
|
|
break;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
|
|
|
mode = IMX_DMA_MEMSIZE_16;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
|
|
|
mode = IMX_DMA_MEMSIZE_32;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2012-03-22 13:54:05 +00:00
|
|
|
imxdmac->internal.hw_chaining = 1;
|
|
|
|
if (!imxdma_hw_chain(&imxdmac->internal))
|
|
|
|
return -EINVAL;
|
2012-03-22 13:54:06 +00:00
|
|
|
imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
|
2012-03-22 13:54:05 +00:00
|
|
|
((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
|
|
|
|
CCR_REN;
|
2012-03-22 13:54:06 +00:00
|
|
|
imxdmac->ccr_to_device =
|
2012-03-22 13:54:05 +00:00
|
|
|
(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
|
|
|
|
((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
|
|
|
|
imx_dmav1_writel(imxdmac->dma_request,
|
|
|
|
DMA_RSSR(imxdmac->channel));
|
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
/* Set burst length */
|
|
|
|
imx_dmav1_writel(imxdmac->watermark_level * imxdmac->word_size,
|
|
|
|
DMA_BLR(imxdmac->channel));
|
2010-10-06 08:25:55 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static enum dma_status imxdma_tx_status(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie,
|
|
|
|
struct dma_tx_state *txstate)
|
|
|
|
{
|
2012-03-06 22:35:27 +00:00
|
|
|
return dma_cookie_status(chan, cookie, txstate);
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
|
|
|
|
dma_cookie_t cookie;
|
2012-03-02 08:28:47 +00:00
|
|
|
unsigned long flags;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
2012-03-06 22:34:46 +00:00
|
|
|
cookie = dma_cookie_assign(tx);
|
2012-03-02 08:28:47 +00:00
|
|
|
spin_unlock_irqrestore(&imxdmac->lock, flags);
|
2010-10-06 08:25:55 +00:00
|
|
|
|
|
|
|
return cookie;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imxdma_alloc_chan_resources(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
|
|
|
struct imx_dma_data *data = chan->private;
|
|
|
|
|
2012-02-28 16:08:17 +00:00
|
|
|
if (data != NULL)
|
|
|
|
imxdmac->dma_request = data->dma_request;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
|
|
|
|
struct imxdma_desc *desc;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc = kzalloc(sizeof(*desc), GFP_KERNEL);
|
|
|
|
if (!desc)
|
|
|
|
break;
|
|
|
|
__memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
|
|
|
|
dma_async_tx_descriptor_init(&desc->desc, chan);
|
|
|
|
desc->desc.tx_submit = imxdma_tx_submit;
|
|
|
|
/* txd.flags will be overwritten in prep funcs */
|
|
|
|
desc->desc.flags = DMA_CTRL_ACK;
|
|
|
|
desc->status = DMA_SUCCESS;
|
|
|
|
|
|
|
|
list_add_tail(&desc->node, &imxdmac->ld_free);
|
|
|
|
imxdmac->descs_allocated++;
|
|
|
|
}
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
if (!imxdmac->descs_allocated)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return imxdmac->descs_allocated;
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void imxdma_free_chan_resources(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
2012-03-02 08:28:47 +00:00
|
|
|
struct imxdma_desc *desc, *_desc;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
imxdma_disable_hw(imxdmac);
|
2012-03-02 08:28:47 +00:00
|
|
|
list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
|
|
|
|
list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&imxdmac->lock, flags);
|
|
|
|
|
|
|
|
list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
|
|
|
|
kfree(desc);
|
|
|
|
imxdmac->descs_allocated--;
|
|
|
|
}
|
|
|
|
INIT_LIST_HEAD(&imxdmac->ld_free);
|
2010-10-06 08:25:55 +00:00
|
|
|
|
|
|
|
if (imxdmac->sg_list) {
|
|
|
|
kfree(imxdmac->sg_list);
|
|
|
|
imxdmac->sg_list = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
2011-10-13 17:04:23 +00:00
|
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
2012-03-08 20:35:13 +00:00
|
|
|
unsigned long flags, void *context)
|
2010-10-06 08:25:55 +00:00
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
|
|
|
struct scatterlist *sg;
|
2012-03-02 08:28:47 +00:00
|
|
|
int i, dma_length = 0;
|
|
|
|
struct imxdma_desc *desc;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
if (list_empty(&imxdmac->ld_free) ||
|
|
|
|
imxdma_chan_is_doing_cyclic(imxdmac))
|
2010-10-06 08:25:55 +00:00
|
|
|
return NULL;
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
|
2010-10-06 08:25:55 +00:00
|
|
|
|
|
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
|
|
dma_length += sg->length;
|
|
|
|
}
|
|
|
|
|
2011-01-12 13:13:23 +00:00
|
|
|
switch (imxdmac->word_size) {
|
|
|
|
case DMA_SLAVE_BUSWIDTH_4_BYTES:
|
|
|
|
if (sgl->length & 3 || sgl->dma_address & 3)
|
|
|
|
return NULL;
|
|
|
|
break;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_2_BYTES:
|
|
|
|
if (sgl->length & 1 || sgl->dma_address & 1)
|
|
|
|
return NULL;
|
|
|
|
break;
|
|
|
|
case DMA_SLAVE_BUSWIDTH_1_BYTE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc->type = IMXDMA_DESC_SLAVE_SG;
|
|
|
|
desc->sg = sgl;
|
|
|
|
desc->sgcount = sg_len;
|
|
|
|
desc->len = dma_length;
|
2012-03-22 13:54:03 +00:00
|
|
|
desc->direction = direction;
|
2012-03-02 08:28:47 +00:00
|
|
|
if (direction == DMA_DEV_TO_MEM) {
|
|
|
|
desc->src = imxdmac->per_address;
|
|
|
|
} else {
|
|
|
|
desc->dest = imxdmac->per_address;
|
|
|
|
}
|
|
|
|
desc->desc.callback = NULL;
|
|
|
|
desc->desc.callback_param = NULL;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
return &desc->desc;
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
|
|
|
|
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
2012-03-08 20:35:13 +00:00
|
|
|
size_t period_len, enum dma_transfer_direction direction,
|
|
|
|
void *context)
|
2010-10-06 08:25:55 +00:00
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
|
|
|
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
2012-03-02 08:28:47 +00:00
|
|
|
struct imxdma_desc *desc;
|
|
|
|
int i;
|
2010-10-06 08:25:55 +00:00
|
|
|
unsigned int periods = buf_len / period_len;
|
|
|
|
|
|
|
|
dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
|
|
|
|
__func__, imxdmac->channel, buf_len, period_len);
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
if (list_empty(&imxdmac->ld_free) ||
|
|
|
|
imxdma_chan_is_doing_cyclic(imxdmac))
|
2010-10-06 08:25:55 +00:00
|
|
|
return NULL;
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
|
2010-10-06 08:25:55 +00:00
|
|
|
|
|
|
|
if (imxdmac->sg_list)
|
|
|
|
kfree(imxdmac->sg_list);
|
|
|
|
|
|
|
|
imxdmac->sg_list = kcalloc(periods + 1,
|
|
|
|
sizeof(struct scatterlist), GFP_KERNEL);
|
|
|
|
if (!imxdmac->sg_list)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
sg_init_table(imxdmac->sg_list, periods);
|
|
|
|
|
|
|
|
for (i = 0; i < periods; i++) {
|
|
|
|
imxdmac->sg_list[i].page_link = 0;
|
|
|
|
imxdmac->sg_list[i].offset = 0;
|
|
|
|
imxdmac->sg_list[i].dma_address = dma_addr;
|
|
|
|
imxdmac->sg_list[i].length = period_len;
|
|
|
|
dma_addr += period_len;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* close the loop */
|
|
|
|
imxdmac->sg_list[periods].offset = 0;
|
|
|
|
imxdmac->sg_list[periods].length = 0;
|
|
|
|
imxdmac->sg_list[periods].page_link =
|
|
|
|
((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc->type = IMXDMA_DESC_CYCLIC;
|
|
|
|
desc->sg = imxdmac->sg_list;
|
|
|
|
desc->sgcount = periods;
|
|
|
|
desc->len = IMX_DMA_LENGTH_LOOP;
|
2012-03-22 13:54:03 +00:00
|
|
|
desc->direction = direction;
|
2012-03-02 08:28:47 +00:00
|
|
|
if (direction == DMA_DEV_TO_MEM) {
|
|
|
|
desc->src = imxdmac->per_address;
|
|
|
|
} else {
|
|
|
|
desc->dest = imxdmac->per_address;
|
|
|
|
}
|
|
|
|
desc->desc.callback = NULL;
|
|
|
|
desc->desc.callback_param = NULL;
|
2010-10-06 08:25:55 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
return &desc->desc;
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
2012-02-28 16:08:17 +00:00
|
|
|
static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
|
|
|
|
struct dma_chan *chan, dma_addr_t dest,
|
|
|
|
dma_addr_t src, size_t len, unsigned long flags)
|
|
|
|
{
|
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
|
|
|
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
2012-03-02 08:28:47 +00:00
|
|
|
struct imxdma_desc *desc;
|
2012-02-28 16:08:17 +00:00
|
|
|
|
|
|
|
dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
|
|
|
|
__func__, imxdmac->channel, src, dest, len);
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
if (list_empty(&imxdmac->ld_free) ||
|
|
|
|
imxdma_chan_is_doing_cyclic(imxdmac))
|
2012-02-28 16:08:17 +00:00
|
|
|
return NULL;
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
|
2012-02-28 16:08:17 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
desc->type = IMXDMA_DESC_MEMCPY;
|
|
|
|
desc->src = src;
|
|
|
|
desc->dest = dest;
|
|
|
|
desc->len = len;
|
2012-03-22 13:54:03 +00:00
|
|
|
desc->direction = DMA_MEM_TO_MEM;
|
2012-03-02 08:28:47 +00:00
|
|
|
desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
|
|
|
|
desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
|
|
|
|
desc->desc.callback = NULL;
|
|
|
|
desc->desc.callback_param = NULL;
|
2012-02-28 16:08:17 +00:00
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
return &desc->desc;
|
2012-02-28 16:08:17 +00:00
|
|
|
}
|
|
|
|
|
2010-10-06 08:25:55 +00:00
|
|
|
static void imxdma_issue_pending(struct dma_chan *chan)
|
|
|
|
{
|
2012-01-09 09:32:49 +00:00
|
|
|
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
2012-03-02 08:28:47 +00:00
|
|
|
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
|
|
|
struct imxdma_desc *desc;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&imxdmac->lock, flags);
|
|
|
|
if (list_empty(&imxdmac->ld_active) &&
|
|
|
|
!list_empty(&imxdmac->ld_queue)) {
|
|
|
|
desc = list_first_entry(&imxdmac->ld_queue,
|
|
|
|
struct imxdma_desc, node);
|
|
|
|
|
|
|
|
if (imxdma_xfer_desc(desc) < 0) {
|
|
|
|
dev_warn(imxdma->dev,
|
|
|
|
"%s: channel: %d couldn't issue DMA xfer\n",
|
|
|
|
__func__, imxdmac->channel);
|
|
|
|
} else {
|
|
|
|
list_move_tail(imxdmac->ld_queue.next,
|
|
|
|
&imxdmac->ld_active);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&imxdmac->lock, flags);
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int __init imxdma_probe(struct platform_device *pdev)
|
2012-03-22 13:54:01 +00:00
|
|
|
{
|
2010-10-06 08:25:55 +00:00
|
|
|
struct imxdma_engine *imxdma;
|
|
|
|
int ret, i;
|
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
if (cpu_is_mx1())
|
|
|
|
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
|
|
|
|
else if (cpu_is_mx21())
|
|
|
|
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
|
|
|
|
else if (cpu_is_mx27())
|
|
|
|
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dma_clk = clk_get(NULL, "dma");
|
|
|
|
if (IS_ERR(dma_clk))
|
|
|
|
return PTR_ERR(dma_clk);
|
|
|
|
clk_enable(dma_clk);
|
|
|
|
|
|
|
|
/* reset DMA module */
|
|
|
|
imx_dmav1_writel(DCR_DRST, DMA_DCR);
|
|
|
|
|
|
|
|
if (cpu_is_mx1()) {
|
|
|
|
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
|
|
|
|
if (ret) {
|
|
|
|
pr_crit("Can't register IRQ for DMA\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
|
|
|
|
if (ret) {
|
|
|
|
pr_crit("Can't register ERRIRQ for DMA\n");
|
|
|
|
free_irq(MX1_DMA_INT, NULL);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* enable DMA module */
|
|
|
|
imx_dmav1_writel(DCR_DEN, DMA_DCR);
|
|
|
|
|
|
|
|
/* clear all interrupts */
|
|
|
|
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
|
|
|
|
|
|
|
|
/* disable interrupts */
|
|
|
|
imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
|
|
|
|
|
2010-10-06 08:25:55 +00:00
|
|
|
imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
|
|
|
|
if (!imxdma)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&imxdma->dma_device.channels);
|
|
|
|
|
2011-01-31 10:35:59 +00:00
|
|
|
dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
|
|
|
|
dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
|
2012-02-28 16:08:17 +00:00
|
|
|
dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
|
2011-01-31 10:35:59 +00:00
|
|
|
|
2010-10-06 08:25:55 +00:00
|
|
|
/* Initialize channel parameters */
|
2012-03-22 13:54:01 +00:00
|
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++) {
|
2010-10-06 08:25:55 +00:00
|
|
|
struct imxdma_channel *imxdmac = &imxdma->channel[i];
|
2012-03-22 13:54:01 +00:00
|
|
|
memset(&imxdmac->internal, 0, sizeof(imxdmac->internal));
|
|
|
|
if (cpu_is_mx21() || cpu_is_mx27()) {
|
|
|
|
ret = request_irq(MX2x_INT_DMACH0 + i,
|
|
|
|
dma_irq_handler, 0, "DMA", imxdma);
|
|
|
|
if (ret) {
|
|
|
|
pr_crit("Can't register IRQ %d for DMA channel %d\n",
|
|
|
|
MX2x_INT_DMACH0 + i, i);
|
|
|
|
goto err_init;
|
|
|
|
}
|
|
|
|
init_timer(&imxdmac->internal.watchdog);
|
|
|
|
imxdmac->internal.watchdog.function = &imxdma_watchdog;
|
|
|
|
imxdmac->internal.watchdog.data = (unsigned long)imxdmac;
|
2010-10-20 06:37:19 +00:00
|
|
|
}
|
2010-10-06 08:25:55 +00:00
|
|
|
|
|
|
|
imxdmac->imxdma = imxdma;
|
|
|
|
spin_lock_init(&imxdmac->lock);
|
|
|
|
|
2012-03-02 08:28:47 +00:00
|
|
|
INIT_LIST_HEAD(&imxdmac->ld_queue);
|
|
|
|
INIT_LIST_HEAD(&imxdmac->ld_free);
|
|
|
|
INIT_LIST_HEAD(&imxdmac->ld_active);
|
|
|
|
|
|
|
|
tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
|
|
|
|
(unsigned long)imxdmac);
|
2010-10-06 08:25:55 +00:00
|
|
|
imxdmac->chan.device = &imxdma->dma_device;
|
2012-03-06 22:36:27 +00:00
|
|
|
dma_cookie_init(&imxdmac->chan);
|
2010-10-06 08:25:55 +00:00
|
|
|
imxdmac->channel = i;
|
|
|
|
|
|
|
|
/* Add the channel to the DMAC list */
|
2012-03-02 08:28:47 +00:00
|
|
|
list_add_tail(&imxdmac->chan.device_node,
|
|
|
|
&imxdma->dma_device.channels);
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
imxdma->dev = &pdev->dev;
|
|
|
|
imxdma->dma_device.dev = &pdev->dev;
|
|
|
|
|
|
|
|
imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
|
|
|
|
imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
|
|
|
|
imxdma->dma_device.device_tx_status = imxdma_tx_status;
|
|
|
|
imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
|
|
|
|
imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
|
2012-02-28 16:08:17 +00:00
|
|
|
imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
|
2010-10-06 08:25:55 +00:00
|
|
|
imxdma->dma_device.device_control = imxdma_control;
|
|
|
|
imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, imxdma);
|
|
|
|
|
2012-02-28 16:08:17 +00:00
|
|
|
imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
|
2011-01-12 12:14:37 +00:00
|
|
|
imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
|
|
|
|
dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
|
|
|
|
|
2010-10-06 08:25:55 +00:00
|
|
|
ret = dma_async_device_register(&imxdma->dma_device);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "unable to register\n");
|
|
|
|
goto err_init;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_init:
|
2012-03-22 13:54:01 +00:00
|
|
|
|
|
|
|
if (cpu_is_mx21() || cpu_is_mx27()) {
|
|
|
|
while (--i >= 0)
|
|
|
|
free_irq(MX2x_INT_DMACH0 + i, NULL);
|
|
|
|
} else if cpu_is_mx1() {
|
|
|
|
free_irq(MX1_DMA_INT, NULL);
|
|
|
|
free_irq(MX1_DMA_ERR, NULL);
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
kfree(imxdma);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __exit imxdma_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dma_async_device_unregister(&imxdma->dma_device);
|
|
|
|
|
2012-03-22 13:54:01 +00:00
|
|
|
if (cpu_is_mx21() || cpu_is_mx27()) {
|
|
|
|
for (i = 0; i < IMX_DMA_CHANNELS; i++)
|
|
|
|
free_irq(MX2x_INT_DMACH0 + i, NULL);
|
|
|
|
} else if cpu_is_mx1() {
|
|
|
|
free_irq(MX1_DMA_INT, NULL);
|
|
|
|
free_irq(MX1_DMA_ERR, NULL);
|
2010-10-06 08:25:55 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
kfree(imxdma);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver imxdma_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "imx-dma",
|
|
|
|
},
|
|
|
|
.remove = __exit_p(imxdma_remove),
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init imxdma_module_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_probe(&imxdma_driver, imxdma_probe);
|
|
|
|
}
|
|
|
|
subsys_initcall(imxdma_module_init);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
|
|
|
|
MODULE_DESCRIPTION("i.MX dma driver");
|
|
|
|
MODULE_LICENSE("GPL");
|