2009-08-20 12:01:05 +00:00
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/*
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* Fifo-attached Serial Interface (FSI) support for SH7724
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on ssi.c
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* Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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2009-11-30 11:24:48 +00:00
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#include <linux/pm_runtime.h>
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2009-08-20 12:01:05 +00:00
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#include <linux/io.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-08-20 12:01:05 +00:00
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#include <sound/soc.h>
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#include <sound/sh_fsi.h>
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#define DO_FMT 0x0000
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#define DOFF_CTL 0x0004
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#define DOFF_ST 0x0008
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#define DI_FMT 0x000C
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#define DIFF_CTL 0x0010
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#define DIFF_ST 0x0014
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#define CKG1 0x0018
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#define CKG2 0x001C
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#define DIDT 0x0020
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#define DODT 0x0024
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#define MUTE_ST 0x0028
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#define REG_END MUTE_ST
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2010-03-25 10:15:53 +00:00
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#define CPU_INT_ST 0x01F4
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#define CPU_IEMSK 0x01F8
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#define CPU_IMSK 0x01FC
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2009-08-20 12:01:05 +00:00
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#define INT_ST 0x0200
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#define IEMSK 0x0204
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#define IMSK 0x0208
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#define MUTE 0x020C
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#define CLK_RST 0x0210
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#define SOFT_RST 0x0214
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2010-03-25 10:15:51 +00:00
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#define FIFO_SZ 0x0218
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2010-03-25 10:15:53 +00:00
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#define MREG_START CPU_INT_ST
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2010-03-25 10:15:51 +00:00
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#define MREG_END FIFO_SZ
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2009-08-20 12:01:05 +00:00
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/* DO_FMT */
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/* DI_FMT */
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2010-07-13 03:13:00 +00:00
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#define CR_MONO (0x0 << 4)
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#define CR_MONO_D (0x1 << 4)
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#define CR_PCM (0x2 << 4)
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#define CR_I2S (0x3 << 4)
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#define CR_TDM (0x4 << 4)
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#define CR_TDM_D (0x5 << 4)
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2009-08-20 12:01:05 +00:00
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/* DOFF_CTL */
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/* DIFF_CTL */
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#define IRQ_HALF 0x00100000
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#define FIFO_CLR 0x00000001
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/* DOFF_ST */
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#define ERR_OVER 0x00000010
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#define ERR_UNDER 0x00000001
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2009-12-28 05:09:16 +00:00
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#define ST_ERR (ERR_OVER | ERR_UNDER)
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2009-08-20 12:01:05 +00:00
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/* CLK_RST */
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#define B_CLK 0x00000010
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#define A_CLK 0x00000001
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/* INT_ST */
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#define INT_B_IN (1 << 12)
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#define INT_B_OUT (1 << 8)
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#define INT_A_IN (1 << 4)
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#define INT_A_OUT (1 << 0)
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2010-03-24 06:27:24 +00:00
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/* SOFT_RST */
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#define PBSR (1 << 12) /* Port B Software Reset */
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#define PASR (1 << 8) /* Port A Software Reset */
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#define IR (1 << 4) /* Interrupt Reset */
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#define FSISR (1 << 0) /* Software Reset */
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2010-03-25 10:15:51 +00:00
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/* FIFO_SZ */
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#define OUT_SZ_MASK 0x7
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#define BO_SZ_SHIFT 8
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#define AO_SZ_SHIFT 0
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2009-08-20 12:01:05 +00:00
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#define FSI_RATES SNDRV_PCM_RATE_8000_96000
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#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
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/************************************************************************
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struct
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************************************************************************/
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struct fsi_priv {
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void __iomem *base;
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struct snd_pcm_substream *substream;
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2009-12-02 06:11:08 +00:00
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struct fsi_master *master;
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2009-08-20 12:01:05 +00:00
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int fifo_max;
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int chan;
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int byte_offset;
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int period_len;
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int buffer_len;
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int periods;
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};
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2010-07-13 03:13:04 +00:00
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struct fsi_core {
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int ver;
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2010-03-25 10:15:53 +00:00
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u32 int_st;
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u32 iemsk;
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u32 imsk;
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};
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2009-08-20 12:01:05 +00:00
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struct fsi_master {
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void __iomem *base;
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int irq;
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struct fsi_priv fsia;
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struct fsi_priv fsib;
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2010-07-13 03:13:04 +00:00
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struct fsi_core *core;
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2009-08-20 12:01:05 +00:00
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struct sh_fsi_platform_info *info;
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2010-01-28 04:46:16 +00:00
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spinlock_t lock;
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2009-08-20 12:01:05 +00:00
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};
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/************************************************************************
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basic read write function
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************************************************************************/
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2010-02-03 16:37:23 +00:00
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static void __fsi_reg_write(u32 reg, u32 data)
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2009-08-20 12:01:05 +00:00
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{
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/* valid data area is 24bit */
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data &= 0x00ffffff;
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2010-02-03 16:37:23 +00:00
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__raw_writel(data, reg);
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2009-08-20 12:01:05 +00:00
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}
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static u32 __fsi_reg_read(u32 reg)
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{
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2010-02-03 16:37:23 +00:00
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return __raw_readl(reg);
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2009-08-20 12:01:05 +00:00
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}
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2010-02-03 16:37:23 +00:00
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static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
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2009-08-20 12:01:05 +00:00
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{
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u32 val = __fsi_reg_read(reg);
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val &= ~mask;
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val |= data & mask;
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2010-02-03 16:37:23 +00:00
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__fsi_reg_write(reg, val);
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2009-08-20 12:01:05 +00:00
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}
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2010-02-03 16:37:23 +00:00
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static void fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
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2009-08-20 12:01:05 +00:00
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{
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if (reg > REG_END)
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2010-02-03 16:37:23 +00:00
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return;
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2009-08-20 12:01:05 +00:00
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2010-02-03 16:37:23 +00:00
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__fsi_reg_write((u32)(fsi->base + reg), data);
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2009-08-20 12:01:05 +00:00
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}
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static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
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{
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if (reg > REG_END)
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return 0;
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return __fsi_reg_read((u32)(fsi->base + reg));
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}
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2010-02-03 16:37:23 +00:00
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static void fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
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2009-08-20 12:01:05 +00:00
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{
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if (reg > REG_END)
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2010-02-03 16:37:23 +00:00
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return;
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2009-08-20 12:01:05 +00:00
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2010-02-03 16:37:23 +00:00
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__fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
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2009-08-20 12:01:05 +00:00
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}
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2010-02-03 16:37:23 +00:00
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static void fsi_master_write(struct fsi_master *master, u32 reg, u32 data)
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2009-08-20 12:01:05 +00:00
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{
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2010-01-28 04:46:16 +00:00
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unsigned long flags;
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2009-08-20 12:01:05 +00:00
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if ((reg < MREG_START) ||
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(reg > MREG_END))
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2010-02-03 16:37:23 +00:00
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return;
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2009-08-20 12:01:05 +00:00
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2010-01-28 04:46:16 +00:00
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spin_lock_irqsave(&master->lock, flags);
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2010-02-03 16:37:23 +00:00
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__fsi_reg_write((u32)(master->base + reg), data);
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2010-01-28 04:46:16 +00:00
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spin_unlock_irqrestore(&master->lock, flags);
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2009-08-20 12:01:05 +00:00
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}
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2009-12-02 06:11:08 +00:00
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static u32 fsi_master_read(struct fsi_master *master, u32 reg)
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2009-08-20 12:01:05 +00:00
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{
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2010-01-28 04:46:16 +00:00
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u32 ret;
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unsigned long flags;
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2009-08-20 12:01:05 +00:00
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if ((reg < MREG_START) ||
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(reg > MREG_END))
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return 0;
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2010-01-28 04:46:16 +00:00
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spin_lock_irqsave(&master->lock, flags);
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ret = __fsi_reg_read((u32)(master->base + reg));
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spin_unlock_irqrestore(&master->lock, flags);
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return ret;
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2009-08-20 12:01:05 +00:00
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}
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2010-02-03 16:37:23 +00:00
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static void fsi_master_mask_set(struct fsi_master *master,
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2009-12-02 06:11:08 +00:00
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u32 reg, u32 mask, u32 data)
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2009-08-20 12:01:05 +00:00
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{
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2010-01-28 04:46:16 +00:00
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unsigned long flags;
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2009-08-20 12:01:05 +00:00
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if ((reg < MREG_START) ||
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(reg > MREG_END))
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2010-02-03 16:37:23 +00:00
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return;
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2009-08-20 12:01:05 +00:00
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2010-01-28 04:46:16 +00:00
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spin_lock_irqsave(&master->lock, flags);
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2010-02-03 16:37:23 +00:00
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__fsi_reg_mask_set((u32)(master->base + reg), mask, data);
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2010-01-28 04:46:16 +00:00
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spin_unlock_irqrestore(&master->lock, flags);
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2009-08-20 12:01:05 +00:00
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}
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/************************************************************************
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basic function
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************************************************************************/
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2009-12-02 06:11:08 +00:00
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static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
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2009-08-20 12:01:05 +00:00
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{
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2009-12-02 06:11:08 +00:00
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return fsi->master;
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2009-08-20 12:01:05 +00:00
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}
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static int fsi_is_port_a(struct fsi_priv *fsi)
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{
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2009-12-02 06:11:08 +00:00
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return fsi->master->base == fsi->base;
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}
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2009-08-20 12:01:05 +00:00
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2009-12-28 05:09:11 +00:00
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static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
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2009-12-02 06:11:08 +00:00
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai_link *machine = rtd->dai;
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2009-12-28 05:09:11 +00:00
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return machine->cpu_dai;
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}
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static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
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{
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struct snd_soc_dai *dai = fsi_get_dai(substream);
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2009-08-20 12:01:05 +00:00
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2009-12-02 06:11:08 +00:00
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return dai->private_data;
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2009-08-20 12:01:05 +00:00
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}
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static u32 fsi_get_info_flags(struct fsi_priv *fsi)
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{
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int is_porta = fsi_is_port_a(fsi);
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2009-12-02 06:11:08 +00:00
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struct fsi_master *master = fsi_get_master(fsi);
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2009-08-20 12:01:05 +00:00
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return is_porta ? master->info->porta_flags :
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master->info->portb_flags;
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}
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static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
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{
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u32 mode;
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u32 flags = fsi_get_info_flags(fsi);
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|
|
mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
|
|
|
|
|
|
|
|
/* return
|
|
|
|
* 1 : master mode
|
|
|
|
* 0 : slave mode
|
|
|
|
*/
|
|
|
|
|
|
|
|
return (mode & flags) != mode;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
|
|
|
|
{
|
|
|
|
int is_porta = fsi_is_port_a(fsi);
|
|
|
|
u32 data;
|
|
|
|
|
|
|
|
if (is_porta)
|
|
|
|
data = is_play ? (1 << 0) : (1 << 4);
|
|
|
|
else
|
|
|
|
data = is_play ? (1 << 8) : (1 << 12);
|
|
|
|
|
|
|
|
return data;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsi_stream_push(struct fsi_priv *fsi,
|
|
|
|
struct snd_pcm_substream *substream,
|
|
|
|
u32 buffer_len,
|
|
|
|
u32 period_len)
|
|
|
|
{
|
|
|
|
fsi->substream = substream;
|
|
|
|
fsi->buffer_len = buffer_len;
|
|
|
|
fsi->period_len = period_len;
|
|
|
|
fsi->byte_offset = 0;
|
|
|
|
fsi->periods = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsi_stream_pop(struct fsi_priv *fsi)
|
|
|
|
{
|
|
|
|
fsi->substream = NULL;
|
|
|
|
fsi->buffer_len = 0;
|
|
|
|
fsi->period_len = 0;
|
|
|
|
fsi->byte_offset = 0;
|
|
|
|
fsi->periods = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
|
|
|
|
{
|
|
|
|
u32 status;
|
|
|
|
u32 reg = is_play ? DOFF_ST : DIFF_ST;
|
|
|
|
int residue;
|
|
|
|
|
|
|
|
status = fsi_reg_read(fsi, reg);
|
|
|
|
residue = 0x1ff & (status >> 8);
|
|
|
|
residue *= fsi->chan;
|
|
|
|
|
|
|
|
return residue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
2010-03-23 02:47:54 +00:00
|
|
|
irq function
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
|
|
|
static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
|
|
|
|
{
|
|
|
|
u32 data = fsi_port_ab_io_bit(fsi, is_play);
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_master *master = fsi_get_master(fsi);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2010-07-13 03:13:04 +00:00
|
|
|
fsi_master_mask_set(master, master->core->imsk, data, data);
|
|
|
|
fsi_master_mask_set(master, master->core->iemsk, data, data);
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
|
|
|
|
{
|
|
|
|
u32 data = fsi_port_ab_io_bit(fsi, is_play);
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_master *master = fsi_get_master(fsi);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2010-07-13 03:13:04 +00:00
|
|
|
fsi_master_mask_set(master, master->core->imsk, data, 0);
|
|
|
|
fsi_master_mask_set(master, master->core->iemsk, data, 0);
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
2010-03-23 02:47:54 +00:00
|
|
|
static u32 fsi_irq_get_status(struct fsi_master *master)
|
|
|
|
{
|
2010-07-13 03:13:04 +00:00
|
|
|
return fsi_master_read(master, master->core->int_st);
|
2010-03-23 02:47:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void fsi_irq_clear_all_status(struct fsi_master *master)
|
|
|
|
{
|
2010-07-13 03:13:04 +00:00
|
|
|
fsi_master_write(master, master->core->int_st, 0);
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
2010-03-23 02:47:54 +00:00
|
|
|
static void fsi_irq_clear_status(struct fsi_priv *fsi)
|
|
|
|
{
|
|
|
|
u32 data = 0;
|
|
|
|
struct fsi_master *master = fsi_get_master(fsi);
|
|
|
|
|
|
|
|
data |= fsi_port_ab_io_bit(fsi, 0);
|
|
|
|
data |= fsi_port_ab_io_bit(fsi, 1);
|
|
|
|
|
|
|
|
/* clear interrupt factor */
|
2010-07-13 03:13:04 +00:00
|
|
|
fsi_master_mask_set(master, master->core->int_st, data, 0);
|
2010-03-23 02:47:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
|
|
|
ctrl function
|
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
2009-08-20 12:01:05 +00:00
|
|
|
static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
|
|
|
|
{
|
|
|
|
u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_master *master = fsi_get_master(fsi);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
if (enable)
|
2009-12-02 06:11:08 +00:00
|
|
|
fsi_master_mask_set(master, CLK_RST, val, val);
|
2009-08-20 12:01:05 +00:00
|
|
|
else
|
2009-12-02 06:11:08 +00:00
|
|
|
fsi_master_mask_set(master, CLK_RST, val, 0);
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
2010-03-25 10:15:51 +00:00
|
|
|
static void fsi_fifo_init(struct fsi_priv *fsi,
|
|
|
|
int is_play,
|
|
|
|
struct snd_soc_dai *dai)
|
2009-08-20 12:01:05 +00:00
|
|
|
{
|
2010-03-25 10:15:51 +00:00
|
|
|
struct fsi_master *master = fsi_get_master(fsi);
|
|
|
|
u32 ctrl, shift, i;
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2010-03-25 10:15:51 +00:00
|
|
|
/* get on-chip RAM capacity */
|
|
|
|
shift = fsi_master_read(master, FIFO_SZ);
|
|
|
|
shift >>= fsi_is_port_a(fsi) ? AO_SZ_SHIFT : BO_SZ_SHIFT;
|
|
|
|
shift &= OUT_SZ_MASK;
|
|
|
|
fsi->fifo_max = 256 << shift;
|
|
|
|
dev_dbg(dai->dev, "fifo = %d words\n", fsi->fifo_max);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2010-03-25 10:15:51 +00:00
|
|
|
/*
|
|
|
|
* The maximum number of sample data varies depending
|
|
|
|
* on the number of channels selected for the format.
|
|
|
|
*
|
|
|
|
* FIFOs are used in 4-channel units in 3-channel mode
|
|
|
|
* and in 8-channel units in 5- to 7-channel mode
|
|
|
|
* meaning that more FIFOs than the required size of DPRAM
|
|
|
|
* are used.
|
|
|
|
*
|
|
|
|
* ex) if 256 words of DP-RAM is connected
|
|
|
|
* 1 channel: 256 (256 x 1 = 256)
|
|
|
|
* 2 channels: 128 (128 x 2 = 256)
|
|
|
|
* 3 channels: 64 ( 64 x 3 = 192)
|
|
|
|
* 4 channels: 64 ( 64 x 4 = 256)
|
|
|
|
* 5 channels: 32 ( 32 x 5 = 160)
|
|
|
|
* 6 channels: 32 ( 32 x 6 = 192)
|
|
|
|
* 7 channels: 32 ( 32 x 7 = 224)
|
|
|
|
* 8 channels: 32 ( 32 x 8 = 256)
|
|
|
|
*/
|
|
|
|
for (i = 1; i < fsi->chan; i <<= 1)
|
|
|
|
fsi->fifo_max >>= 1;
|
|
|
|
dev_dbg(dai->dev, "%d channel %d store\n", fsi->chan, fsi->fifo_max);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
ctrl = is_play ? DOFF_CTL : DIFF_CTL;
|
|
|
|
|
|
|
|
/* set interrupt generation factor */
|
|
|
|
fsi_reg_write(fsi, ctrl, IRQ_HALF);
|
|
|
|
|
|
|
|
/* clear FIFO */
|
|
|
|
fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
|
|
|
|
}
|
|
|
|
|
2009-12-02 06:11:08 +00:00
|
|
|
static void fsi_soft_all_reset(struct fsi_master *master)
|
2009-08-20 12:01:05 +00:00
|
|
|
{
|
|
|
|
/* port AB reset */
|
2010-03-24 06:27:24 +00:00
|
|
|
fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
|
2009-08-20 12:01:05 +00:00
|
|
|
mdelay(10);
|
|
|
|
|
|
|
|
/* soft reset */
|
2010-03-24 06:27:24 +00:00
|
|
|
fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
|
|
|
|
fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
|
2009-08-20 12:01:05 +00:00
|
|
|
mdelay(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* playback interrupt */
|
2010-02-22 07:41:57 +00:00
|
|
|
static int fsi_data_push(struct fsi_priv *fsi, int startup)
|
2009-08-20 12:01:05 +00:00
|
|
|
{
|
|
|
|
struct snd_pcm_runtime *runtime;
|
|
|
|
struct snd_pcm_substream *substream = NULL;
|
2009-12-28 05:09:16 +00:00
|
|
|
u32 status;
|
2009-08-20 12:01:05 +00:00
|
|
|
int send;
|
|
|
|
int fifo_free;
|
|
|
|
int width;
|
2009-10-30 03:02:39 +00:00
|
|
|
u8 *start;
|
2010-02-22 07:41:57 +00:00
|
|
|
int i, over_period;
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
if (!fsi ||
|
|
|
|
!fsi->substream ||
|
|
|
|
!fsi->substream->runtime)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-12-28 05:09:05 +00:00
|
|
|
over_period = 0;
|
|
|
|
substream = fsi->substream;
|
|
|
|
runtime = substream->runtime;
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
/* FSI FIFO has limit.
|
|
|
|
* So, this driver can not send periods data at a time
|
|
|
|
*/
|
|
|
|
if (fsi->byte_offset >=
|
|
|
|
fsi->period_len * (fsi->periods + 1)) {
|
|
|
|
|
2009-12-28 05:09:05 +00:00
|
|
|
over_period = 1;
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi->periods = (fsi->periods + 1) % runtime->periods;
|
|
|
|
|
|
|
|
if (0 == fsi->periods)
|
|
|
|
fsi->byte_offset = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* get 1 channel data width */
|
|
|
|
width = frames_to_bytes(runtime, 1) / fsi->chan;
|
|
|
|
|
|
|
|
/* get send size for alsa */
|
|
|
|
send = (fsi->buffer_len - fsi->byte_offset) / width;
|
|
|
|
|
|
|
|
/* get FIFO free size */
|
|
|
|
fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
|
|
|
|
|
|
|
|
/* size check */
|
|
|
|
if (fifo_free < send)
|
|
|
|
send = fifo_free;
|
|
|
|
|
2009-10-30 03:02:39 +00:00
|
|
|
start = runtime->dma_area;
|
|
|
|
start += fsi->byte_offset;
|
|
|
|
|
|
|
|
switch (width) {
|
|
|
|
case 2:
|
|
|
|
for (i = 0; i < send; i++)
|
|
|
|
fsi_reg_write(fsi, DODT,
|
|
|
|
((u32)*((u16 *)start + i) << 8));
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
for (i = 0; i < send; i++)
|
|
|
|
fsi_reg_write(fsi, DODT, *((u32 *)start + i));
|
|
|
|
break;
|
|
|
|
default:
|
2009-08-20 12:01:05 +00:00
|
|
|
return -EINVAL;
|
2009-10-30 03:02:39 +00:00
|
|
|
}
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
fsi->byte_offset += send * width;
|
|
|
|
|
2009-12-28 05:09:16 +00:00
|
|
|
status = fsi_reg_read(fsi, DOFF_ST);
|
2010-02-22 07:41:57 +00:00
|
|
|
if (!startup) {
|
2009-12-28 05:09:16 +00:00
|
|
|
struct snd_soc_dai *dai = fsi_get_dai(substream);
|
2010-02-22 07:41:57 +00:00
|
|
|
|
|
|
|
if (status & ERR_OVER)
|
|
|
|
dev_err(dai->dev, "over run\n");
|
|
|
|
if (status & ERR_UNDER)
|
|
|
|
dev_err(dai->dev, "under run\n");
|
2009-12-28 05:09:16 +00:00
|
|
|
}
|
2010-02-22 07:41:57 +00:00
|
|
|
fsi_reg_write(fsi, DOFF_ST, 0);
|
2009-12-28 05:09:16 +00:00
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi_irq_enable(fsi, 1);
|
|
|
|
|
2009-12-28 05:09:05 +00:00
|
|
|
if (over_period)
|
2009-08-20 12:01:05 +00:00
|
|
|
snd_pcm_period_elapsed(substream);
|
|
|
|
|
2010-02-22 07:41:57 +00:00
|
|
|
return 0;
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
2010-02-22 07:41:57 +00:00
|
|
|
static int fsi_data_pop(struct fsi_priv *fsi, int startup)
|
2009-10-30 03:02:44 +00:00
|
|
|
{
|
|
|
|
struct snd_pcm_runtime *runtime;
|
|
|
|
struct snd_pcm_substream *substream = NULL;
|
2009-12-28 05:09:16 +00:00
|
|
|
u32 status;
|
2009-10-30 03:02:44 +00:00
|
|
|
int free;
|
|
|
|
int fifo_fill;
|
|
|
|
int width;
|
|
|
|
u8 *start;
|
2010-02-22 07:41:57 +00:00
|
|
|
int i, over_period;
|
2009-10-30 03:02:44 +00:00
|
|
|
|
|
|
|
if (!fsi ||
|
|
|
|
!fsi->substream ||
|
|
|
|
!fsi->substream->runtime)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2009-12-28 05:09:05 +00:00
|
|
|
over_period = 0;
|
|
|
|
substream = fsi->substream;
|
|
|
|
runtime = substream->runtime;
|
2009-10-30 03:02:44 +00:00
|
|
|
|
|
|
|
/* FSI FIFO has limit.
|
|
|
|
* So, this driver can not send periods data at a time
|
|
|
|
*/
|
|
|
|
if (fsi->byte_offset >=
|
|
|
|
fsi->period_len * (fsi->periods + 1)) {
|
|
|
|
|
2009-12-28 05:09:05 +00:00
|
|
|
over_period = 1;
|
2009-10-30 03:02:44 +00:00
|
|
|
fsi->periods = (fsi->periods + 1) % runtime->periods;
|
|
|
|
|
|
|
|
if (0 == fsi->periods)
|
|
|
|
fsi->byte_offset = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* get 1 channel data width */
|
|
|
|
width = frames_to_bytes(runtime, 1) / fsi->chan;
|
|
|
|
|
|
|
|
/* get free space for alsa */
|
|
|
|
free = (fsi->buffer_len - fsi->byte_offset) / width;
|
|
|
|
|
|
|
|
/* get recv size */
|
|
|
|
fifo_fill = fsi_get_fifo_residue(fsi, 0);
|
|
|
|
|
|
|
|
if (free < fifo_fill)
|
|
|
|
fifo_fill = free;
|
|
|
|
|
|
|
|
start = runtime->dma_area;
|
|
|
|
start += fsi->byte_offset;
|
|
|
|
|
|
|
|
switch (width) {
|
|
|
|
case 2:
|
|
|
|
for (i = 0; i < fifo_fill; i++)
|
|
|
|
*((u16 *)start + i) =
|
|
|
|
(u16)(fsi_reg_read(fsi, DIDT) >> 8);
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
for (i = 0; i < fifo_fill; i++)
|
|
|
|
*((u32 *)start + i) = fsi_reg_read(fsi, DIDT);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
fsi->byte_offset += fifo_fill * width;
|
|
|
|
|
2009-12-28 05:09:16 +00:00
|
|
|
status = fsi_reg_read(fsi, DIFF_ST);
|
2010-02-22 07:41:57 +00:00
|
|
|
if (!startup) {
|
2009-12-28 05:09:16 +00:00
|
|
|
struct snd_soc_dai *dai = fsi_get_dai(substream);
|
2010-02-22 07:41:57 +00:00
|
|
|
|
|
|
|
if (status & ERR_OVER)
|
|
|
|
dev_err(dai->dev, "over run\n");
|
|
|
|
if (status & ERR_UNDER)
|
|
|
|
dev_err(dai->dev, "under run\n");
|
2009-12-28 05:09:16 +00:00
|
|
|
}
|
2010-02-22 07:41:57 +00:00
|
|
|
fsi_reg_write(fsi, DIFF_ST, 0);
|
2009-12-28 05:09:16 +00:00
|
|
|
|
2009-10-30 03:02:44 +00:00
|
|
|
fsi_irq_enable(fsi, 0);
|
|
|
|
|
2009-12-28 05:09:05 +00:00
|
|
|
if (over_period)
|
2009-10-30 03:02:44 +00:00
|
|
|
snd_pcm_period_elapsed(substream);
|
|
|
|
|
2010-02-22 07:41:57 +00:00
|
|
|
return 0;
|
2009-10-30 03:02:44 +00:00
|
|
|
}
|
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
static irqreturn_t fsi_interrupt(int irq, void *data)
|
|
|
|
{
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_master *master = data;
|
2010-03-23 02:47:54 +00:00
|
|
|
u32 int_st = fsi_irq_get_status(master);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
/* clear irq status */
|
2010-03-24 06:27:24 +00:00
|
|
|
fsi_master_mask_set(master, SOFT_RST, IR, 0);
|
|
|
|
fsi_master_mask_set(master, SOFT_RST, IR, IR);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
if (int_st & INT_A_OUT)
|
2010-02-22 07:41:57 +00:00
|
|
|
fsi_data_push(&master->fsia, 0);
|
2009-08-20 12:01:05 +00:00
|
|
|
if (int_st & INT_B_OUT)
|
2010-02-22 07:41:57 +00:00
|
|
|
fsi_data_push(&master->fsib, 0);
|
2009-10-30 03:02:44 +00:00
|
|
|
if (int_st & INT_A_IN)
|
2010-02-22 07:41:57 +00:00
|
|
|
fsi_data_pop(&master->fsia, 0);
|
2009-10-30 03:02:44 +00:00
|
|
|
if (int_st & INT_B_IN)
|
2010-02-22 07:41:57 +00:00
|
|
|
fsi_data_pop(&master->fsib, 0);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2010-03-23 02:47:54 +00:00
|
|
|
fsi_irq_clear_all_status(master);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
|
|
|
dai ops
|
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
|
|
|
static int fsi_dai_startup(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_priv *fsi = fsi_get_priv(substream);
|
2009-08-20 12:01:05 +00:00
|
|
|
u32 flags = fsi_get_info_flags(fsi);
|
|
|
|
u32 fmt;
|
|
|
|
u32 reg;
|
|
|
|
u32 data;
|
|
|
|
int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
|
|
|
int is_master;
|
|
|
|
int ret = 0;
|
|
|
|
|
2009-11-30 11:24:48 +00:00
|
|
|
pm_runtime_get_sync(dai->dev);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
/* CKG1 */
|
|
|
|
data = is_play ? (1 << 0) : (1 << 4);
|
|
|
|
is_master = fsi_is_master_mode(fsi, is_play);
|
|
|
|
if (is_master)
|
|
|
|
fsi_reg_mask_set(fsi, CKG1, data, data);
|
|
|
|
else
|
|
|
|
fsi_reg_mask_set(fsi, CKG1, data, 0);
|
|
|
|
|
|
|
|
/* clock inversion (CKG2) */
|
|
|
|
data = 0;
|
2010-07-13 03:01:15 +00:00
|
|
|
if (SH_FSI_LRM_INV & flags)
|
|
|
|
data |= 1 << 12;
|
|
|
|
if (SH_FSI_BRM_INV & flags)
|
|
|
|
data |= 1 << 8;
|
|
|
|
if (SH_FSI_LRS_INV & flags)
|
|
|
|
data |= 1 << 4;
|
|
|
|
if (SH_FSI_BRS_INV & flags)
|
|
|
|
data |= 1 << 0;
|
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi_reg_write(fsi, CKG2, data);
|
|
|
|
|
|
|
|
/* do fmt, di fmt */
|
|
|
|
data = 0;
|
|
|
|
reg = is_play ? DO_FMT : DI_FMT;
|
|
|
|
fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
|
|
|
|
switch (fmt) {
|
|
|
|
case SH_FSI_FMT_MONO:
|
2010-07-13 03:13:00 +00:00
|
|
|
data = CR_MONO;
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi->chan = 1;
|
|
|
|
break;
|
|
|
|
case SH_FSI_FMT_MONO_DELAY:
|
2010-07-13 03:13:00 +00:00
|
|
|
data = CR_MONO_D;
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi->chan = 1;
|
|
|
|
break;
|
|
|
|
case SH_FSI_FMT_PCM:
|
2010-07-13 03:13:00 +00:00
|
|
|
data = CR_PCM;
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi->chan = 2;
|
|
|
|
break;
|
|
|
|
case SH_FSI_FMT_I2S:
|
2010-07-13 03:13:00 +00:00
|
|
|
data = CR_I2S;
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi->chan = 2;
|
|
|
|
break;
|
|
|
|
case SH_FSI_FMT_TDM:
|
|
|
|
fsi->chan = is_play ?
|
|
|
|
SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
|
2010-07-13 03:13:00 +00:00
|
|
|
data = CR_TDM | (fsi->chan - 1);
|
2009-08-20 12:01:05 +00:00
|
|
|
break;
|
|
|
|
case SH_FSI_FMT_TDM_DELAY:
|
|
|
|
fsi->chan = is_play ?
|
|
|
|
SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
|
2010-07-13 03:13:00 +00:00
|
|
|
data = CR_TDM_D | (fsi->chan - 1);
|
2009-08-20 12:01:05 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dai->dev, "unknown format.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
fsi_reg_write(fsi, reg, data);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* clear clk reset if master mode
|
|
|
|
*/
|
|
|
|
if (is_master)
|
|
|
|
fsi_clk_ctrl(fsi, 1);
|
|
|
|
|
2010-03-23 02:47:54 +00:00
|
|
|
/* irq clear */
|
|
|
|
fsi_irq_disable(fsi, is_play);
|
|
|
|
fsi_irq_clear_status(fsi);
|
|
|
|
|
|
|
|
/* fifo init */
|
2010-03-25 10:15:51 +00:00
|
|
|
fsi_fifo_init(fsi, is_play, dai);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_priv *fsi = fsi_get_priv(substream);
|
2009-08-20 12:01:05 +00:00
|
|
|
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
|
|
|
|
|
|
|
fsi_irq_disable(fsi, is_play);
|
|
|
|
fsi_clk_ctrl(fsi, 0);
|
|
|
|
|
2009-11-30 11:24:48 +00:00
|
|
|
pm_runtime_put_sync(dai->dev);
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_priv *fsi = fsi_get_priv(substream);
|
2009-08-20 12:01:05 +00:00
|
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
|
|
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
fsi_stream_push(fsi, substream,
|
|
|
|
frames_to_bytes(runtime, runtime->buffer_size),
|
|
|
|
frames_to_bytes(runtime, runtime->period_size));
|
2010-02-22 07:41:57 +00:00
|
|
|
ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
|
2009-08-20 12:01:05 +00:00
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
fsi_irq_disable(fsi, is_play);
|
|
|
|
fsi_stream_pop(fsi);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_soc_dai_ops fsi_dai_ops = {
|
|
|
|
.startup = fsi_dai_startup,
|
|
|
|
.shutdown = fsi_dai_shutdown,
|
|
|
|
.trigger = fsi_dai_trigger,
|
|
|
|
};
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
|
|
|
pcm ops
|
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
|
|
|
static struct snd_pcm_hardware fsi_pcm_hardware = {
|
|
|
|
.info = SNDRV_PCM_INFO_INTERLEAVED |
|
|
|
|
SNDRV_PCM_INFO_MMAP |
|
|
|
|
SNDRV_PCM_INFO_MMAP_VALID |
|
|
|
|
SNDRV_PCM_INFO_PAUSE,
|
|
|
|
.formats = FSI_FMTS,
|
|
|
|
.rates = FSI_RATES,
|
|
|
|
.rate_min = 8000,
|
|
|
|
.rate_max = 192000,
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 2,
|
|
|
|
.buffer_bytes_max = 64 * 1024,
|
|
|
|
.period_bytes_min = 32,
|
|
|
|
.period_bytes_max = 8192,
|
|
|
|
.periods_min = 1,
|
|
|
|
.periods_max = 32,
|
|
|
|
.fifo_size = 256,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int fsi_pcm_open(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
|
|
|
|
|
|
|
|
ret = snd_pcm_hw_constraint_integer(runtime,
|
|
|
|
SNDRV_PCM_HW_PARAM_PERIODS);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsi_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *hw_params)
|
|
|
|
{
|
|
|
|
return snd_pcm_lib_malloc_pages(substream,
|
|
|
|
params_buffer_bytes(hw_params));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsi_hw_free(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
return snd_pcm_lib_free_pages(substream);
|
|
|
|
}
|
|
|
|
|
|
|
|
static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
|
|
|
|
{
|
|
|
|
struct snd_pcm_runtime *runtime = substream->runtime;
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_priv *fsi = fsi_get_priv(substream);
|
2009-08-20 12:01:05 +00:00
|
|
|
long location;
|
|
|
|
|
2009-10-30 03:02:39 +00:00
|
|
|
location = (fsi->byte_offset - 1);
|
2009-08-20 12:01:05 +00:00
|
|
|
if (location < 0)
|
|
|
|
location = 0;
|
|
|
|
|
|
|
|
return bytes_to_frames(runtime, location);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct snd_pcm_ops fsi_pcm_ops = {
|
|
|
|
.open = fsi_pcm_open,
|
|
|
|
.ioctl = snd_pcm_lib_ioctl,
|
|
|
|
.hw_params = fsi_hw_params,
|
|
|
|
.hw_free = fsi_hw_free,
|
|
|
|
.pointer = fsi_pointer,
|
|
|
|
};
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
|
|
|
snd_soc_platform
|
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
|
|
|
#define PREALLOC_BUFFER (32 * 1024)
|
|
|
|
#define PREALLOC_BUFFER_MAX (32 * 1024)
|
|
|
|
|
|
|
|
static void fsi_pcm_free(struct snd_pcm *pcm)
|
|
|
|
{
|
|
|
|
snd_pcm_lib_preallocate_free_for_all(pcm);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsi_pcm_new(struct snd_card *card,
|
|
|
|
struct snd_soc_dai *dai,
|
|
|
|
struct snd_pcm *pcm)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
|
|
|
|
* in MMAP mode (i.e. aplay -M)
|
|
|
|
*/
|
|
|
|
return snd_pcm_lib_preallocate_pages_for_all(
|
|
|
|
pcm,
|
|
|
|
SNDRV_DMA_TYPE_CONTINUOUS,
|
|
|
|
snd_dma_continuous_data(GFP_KERNEL),
|
|
|
|
PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
|
|
|
alsa struct
|
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
|
|
|
struct snd_soc_dai fsi_soc_dai[] = {
|
|
|
|
{
|
|
|
|
.name = "FSIA",
|
|
|
|
.id = 0,
|
|
|
|
.playback = {
|
|
|
|
.rates = FSI_RATES,
|
|
|
|
.formats = FSI_FMTS,
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 8,
|
|
|
|
},
|
2009-10-30 03:02:44 +00:00
|
|
|
.capture = {
|
|
|
|
.rates = FSI_RATES,
|
|
|
|
.formats = FSI_FMTS,
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 8,
|
|
|
|
},
|
2009-08-20 12:01:05 +00:00
|
|
|
.ops = &fsi_dai_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "FSIB",
|
|
|
|
.id = 1,
|
|
|
|
.playback = {
|
|
|
|
.rates = FSI_RATES,
|
|
|
|
.formats = FSI_FMTS,
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 8,
|
|
|
|
},
|
2009-10-30 03:02:44 +00:00
|
|
|
.capture = {
|
|
|
|
.rates = FSI_RATES,
|
|
|
|
.formats = FSI_FMTS,
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 8,
|
|
|
|
},
|
2009-08-20 12:01:05 +00:00
|
|
|
.ops = &fsi_dai_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(fsi_soc_dai);
|
|
|
|
|
|
|
|
struct snd_soc_platform fsi_soc_platform = {
|
|
|
|
.name = "fsi-pcm",
|
|
|
|
.pcm_ops = &fsi_pcm_ops,
|
|
|
|
.pcm_new = fsi_pcm_new,
|
|
|
|
.pcm_free = fsi_pcm_free,
|
|
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(fsi_soc_platform);
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
|
|
|
|
|
|
|
|
platform function
|
|
|
|
|
|
|
|
|
|
|
|
************************************************************************/
|
|
|
|
static int fsi_probe(struct platform_device *pdev)
|
|
|
|
{
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_master *master;
|
2010-03-25 10:15:53 +00:00
|
|
|
const struct platform_device_id *id_entry;
|
2009-08-20 12:01:05 +00:00
|
|
|
struct resource *res;
|
|
|
|
unsigned int irq;
|
|
|
|
int ret;
|
|
|
|
|
2009-12-02 06:11:08 +00:00
|
|
|
if (0 != pdev->id) {
|
|
|
|
dev_err(&pdev->dev, "current fsi support id 0 only now\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2010-03-25 10:15:53 +00:00
|
|
|
id_entry = pdev->id_entry;
|
|
|
|
if (!id_entry) {
|
|
|
|
dev_err(&pdev->dev, "unknown fsi device\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2009-12-16 16:10:09 +00:00
|
|
|
if (!res || (int)irq <= 0) {
|
2009-08-20 12:01:05 +00:00
|
|
|
dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
master = kzalloc(sizeof(*master), GFP_KERNEL);
|
|
|
|
if (!master) {
|
|
|
|
dev_err(&pdev->dev, "Could not allocate master\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
|
|
|
master->base = ioremap_nocache(res->start, resource_size(res));
|
|
|
|
if (!master->base) {
|
|
|
|
ret = -ENXIO;
|
|
|
|
dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
|
|
|
|
goto exit_kfree;
|
|
|
|
}
|
|
|
|
|
|
|
|
master->irq = irq;
|
|
|
|
master->info = pdev->dev.platform_data;
|
|
|
|
master->fsia.base = master->base;
|
2009-12-02 06:11:08 +00:00
|
|
|
master->fsia.master = master;
|
2009-08-20 12:01:05 +00:00
|
|
|
master->fsib.base = master->base + 0x40;
|
2009-12-02 06:11:08 +00:00
|
|
|
master->fsib.master = master;
|
2010-07-13 03:13:04 +00:00
|
|
|
master->core = (struct fsi_core *)id_entry->driver_data;
|
2010-01-28 04:46:16 +00:00
|
|
|
spin_lock_init(&master->lock);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2009-11-30 11:24:48 +00:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
pm_runtime_resume(&pdev->dev);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
fsi_soc_dai[0].dev = &pdev->dev;
|
2009-12-02 06:11:08 +00:00
|
|
|
fsi_soc_dai[0].private_data = &master->fsia;
|
2009-08-20 12:01:05 +00:00
|
|
|
fsi_soc_dai[1].dev = &pdev->dev;
|
2009-12-02 06:11:08 +00:00
|
|
|
fsi_soc_dai[1].private_data = &master->fsib;
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2009-12-02 06:11:08 +00:00
|
|
|
fsi_soft_all_reset(master);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
2010-03-25 10:15:53 +00:00
|
|
|
ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
|
|
|
|
id_entry->name, master);
|
2009-08-20 12:01:05 +00:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "irq request err\n");
|
2009-10-30 03:02:39 +00:00
|
|
|
goto exit_iounmap;
|
2009-08-20 12:01:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = snd_soc_register_platform(&fsi_soc_platform);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "cannot snd soc register\n");
|
|
|
|
goto exit_free_irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
|
|
|
|
|
|
|
|
exit_free_irq:
|
|
|
|
free_irq(irq, master);
|
|
|
|
exit_iounmap:
|
|
|
|
iounmap(master->base);
|
2009-11-30 11:24:48 +00:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2009-08-20 12:01:05 +00:00
|
|
|
exit_kfree:
|
|
|
|
kfree(master);
|
|
|
|
master = NULL;
|
|
|
|
exit:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsi_remove(struct platform_device *pdev)
|
|
|
|
{
|
2009-12-02 06:11:08 +00:00
|
|
|
struct fsi_master *master;
|
|
|
|
|
|
|
|
master = fsi_get_master(fsi_soc_dai[0].private_data);
|
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
|
|
|
|
snd_soc_unregister_platform(&fsi_soc_platform);
|
|
|
|
|
2009-11-30 11:24:48 +00:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2009-08-20 12:01:05 +00:00
|
|
|
|
|
|
|
free_irq(master->irq, master);
|
|
|
|
|
|
|
|
iounmap(master->base);
|
|
|
|
kfree(master);
|
2009-12-02 06:11:08 +00:00
|
|
|
|
|
|
|
fsi_soc_dai[0].dev = NULL;
|
|
|
|
fsi_soc_dai[0].private_data = NULL;
|
|
|
|
fsi_soc_dai[1].dev = NULL;
|
|
|
|
fsi_soc_dai[1].private_data = NULL;
|
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-30 11:24:48 +00:00
|
|
|
static int fsi_runtime_nop(struct device *dev)
|
|
|
|
{
|
|
|
|
/* Runtime PM callback shared between ->runtime_suspend()
|
|
|
|
* and ->runtime_resume(). Simply returns success.
|
|
|
|
*
|
|
|
|
* This driver re-initializes all registers after
|
|
|
|
* pm_runtime_get_sync() anyway so there is no need
|
|
|
|
* to save and restore registers here.
|
|
|
|
*/
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct dev_pm_ops fsi_pm_ops = {
|
|
|
|
.runtime_suspend = fsi_runtime_nop,
|
|
|
|
.runtime_resume = fsi_runtime_nop,
|
|
|
|
};
|
|
|
|
|
2010-07-13 03:13:04 +00:00
|
|
|
static struct fsi_core fsi1_core = {
|
|
|
|
.ver = 1,
|
|
|
|
|
|
|
|
/* Interrupt */
|
2010-03-25 10:15:53 +00:00
|
|
|
.int_st = INT_ST,
|
|
|
|
.iemsk = IEMSK,
|
|
|
|
.imsk = IMSK,
|
|
|
|
};
|
|
|
|
|
2010-07-13 03:13:04 +00:00
|
|
|
static struct fsi_core fsi2_core = {
|
|
|
|
.ver = 2,
|
|
|
|
|
|
|
|
/* Interrupt */
|
2010-03-25 10:15:53 +00:00
|
|
|
.int_st = CPU_INT_ST,
|
|
|
|
.iemsk = CPU_IEMSK,
|
|
|
|
.imsk = CPU_IMSK,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device_id fsi_id_table[] = {
|
2010-07-13 03:13:04 +00:00
|
|
|
{ "sh_fsi", (kernel_ulong_t)&fsi1_core },
|
|
|
|
{ "sh_fsi2", (kernel_ulong_t)&fsi2_core },
|
2010-03-25 10:15:53 +00:00
|
|
|
};
|
|
|
|
|
2009-08-20 12:01:05 +00:00
|
|
|
static struct platform_driver fsi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "sh_fsi",
|
2009-11-30 11:24:48 +00:00
|
|
|
.pm = &fsi_pm_ops,
|
2009-08-20 12:01:05 +00:00
|
|
|
},
|
|
|
|
.probe = fsi_probe,
|
|
|
|
.remove = fsi_remove,
|
2010-03-25 10:15:53 +00:00
|
|
|
.id_table = fsi_id_table,
|
2009-08-20 12:01:05 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init fsi_mobile_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&fsi_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit fsi_mobile_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&fsi_driver);
|
|
|
|
}
|
|
|
|
module_init(fsi_mobile_init);
|
|
|
|
module_exit(fsi_mobile_exit);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
|
|
|
|
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
|